Patent application number | Description | Published |
20130026609 | PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE WITH STRESS RELIEF STRUCTURE - An apparatus configured to be coupled onto a substrate, wherein the apparatus comprises a semiconductor substrate and the semiconductor substrate includes a plurality of trenches defined within a side of the semiconductor substrate. The apparatus further comprises an interconnect layer over portions of the side of the semiconductor substrate, wherein the portions of the side of the semiconductor substrate include the plurality of trenches defined within the side of the semiconductor substrate. Each trench is configured to respectively receive a solder ball to provide an interface between i) the interconnect layer and ii) the substrate to which the apparatus is to be coupled. | 01-31-2013 |
20130031432 | FULLY-BUFFERED DUAL IN-LINE MEMORY MODULE WITH FAULT CORRECTION - A memory circuit including a logic circuit, content addressable memory, and a multiplexer. The logic circuit is configured to output a first address. The content addressable memory is configured to i) receive the first address and ii) output a substitute address and a match signal if the first address matches a second address stored in the content addressable memory. The multiplexer is configured to i) receive the first address and the substitute address and ii) selectively output one of the first address and the substitute address based on the match signal. | 01-31-2013 |
20130039427 | Method and Apparatus for Periodic Structure Handling for Motion Compensation - A motion compensated picture rate converter for determining a dominant motion vector for a block appearing in two images includes a high-pass filter and a low-pass filter, transform calculators responsive to the filters for performing transforms on at least two images to produce a frequency-domain representation of the images, estimating calculators for estimating a plurality of motion vectors based on the frequency-domain representations, and a periodic structure detection and elimination module responsive to the transform calculators and the estimating calculators for identifying a period based on the frequency-domain representation of the images and for selecting a dominant motion vector based on the estimated motion vectors and the identified period. A method of operation is also disclosed. | 02-14-2013 |
20130044555 | PROCESSOR WITH MEMORY DELAYED BIT LINE PRECHARGING - A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array. | 02-21-2013 |
20130045573 | CHIP ON LEADS - Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated circuit chip onto the bonding fingers may reduce the pin-out count by allowing multiple integrated circuit chips to be interconnected within the same microelectronic package. Other embodiments may be described and claimed. | 02-21-2013 |
20130045687 | Short-Range Wireless Communication - The present specification describes techniques and apparatus that enable wireless devices to communicate effectively at short ranges. In one implementation, the transmit power of a transmitting device is reduced to permit a receiving device to demodulate a signal. | 02-21-2013 |
20130045688 | Short-Range Wireless Communication - The present specification describes techniques and apparatus that enable wireless devices to communicate effectively at short ranges. In one implementation, the transmit power of a transmitting device is reduced to permit a receiving device to demodulate a signal. | 02-21-2013 |
20130046966 | Preloader - This disclosure describes techniques and/or apparatuses for reducing the total time used to boot up a computer and load applications onto the computer. | 02-21-2013 |
20130052966 | System and Transceiver Clocking to Minimize Required Number of Reference Sources in Multi-Function Cellular Applications Including GPS - A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals. | 02-28-2013 |
20130058300 | Uplink Power Control in Aggregated Spectrum Systems - A method for communication includes modulating data in a wireless communication terminal to produce an aggregated-spectrum signal, which includes at least first and second signals in respective first and second spectral bands. The modulated data is transmitted in the first and second signals at respective first and second power levels. The second power level is adjusted separately from the first power level. In some embodiments, one or more instructions to set the first power level are received at the wireless communication terminal, and the first power level is set separately from setting the second power level based on the instructions. | 03-07-2013 |
20130058504 | MULTI-MODE AUDIO AMPLIFIERS - A multimode audio amplifier comprises: a mode controller adapted to provide a control signal; and at least one multimode module, wherein each of the multimode modules has a plurality of operating modes, wherein the operating modes are selected in accordance with the control signal, wherein changing the operating modes results in a measurable change in at least one characteristic of the multimode audio amplifier; wherein the characteristics of the multimode audio amplifier consist of signal to noise ratio (SNR); total harmonic distortion and noise (THD+N); input to output delay; power consumption; and efficiency. | 03-07-2013 |
20130059596 | ASYMMETRICAL FEEDBACK FOR COORDINATED TRANSMISSION SYSTEMS - A method includes, in a mobile communication terminal, receiving from at least first and second base stations, which cooperate in a coordinated transmission scheme, signals that are transmitted over respective first and second communication channels. Respective channel measures are calculated for the communication channels based on the received signals. First and second feedback data, which are indicative of the respective channel measures of the first and second communication channels, are formulated such that the first feedback data has a first data size and the second feedback data has a second data size, different from the first data size. The first and second feedback data are transmitted from the mobile communication terminal to at least one of the base stations. | 03-07-2013 |
20130064060 | METHOD AND APPARATUS FOR DETERMINING A LOCATION OF A FEATURE ON A STORAGE MEDIUM - A change in a property of a signal is detected, the signal having been sensed from a storage medium by a disk drive. A count is determined, the count corresponding to a first location on the storage medium at which the change in the property of the signal sensed from the storage medium is detected. The count is used to predict a second location on the storage medium corresponding to the change in the property of the signal sensed from the storage medium. Relative to the first location on the storage medium, the second location on the storage medium is closer to an actual location of a feature on the storage medium that causes the change in the property of the signal sensed from the storage medium. | 03-14-2013 |
20130077538 | CONFERENCE MIXING USING TURBO-VAD - A conference mixer includes a unit configured to receive a plurality of input streams, a spectral voice activity detection (VAD) unit configured to, for each of the input streams, generate and output a spectral VAD decision indicating whether a frame including data packets is voice, a turbo VAD unit configured to generate and output a turbo VAD decision that indicates for a frame including data packets which input stream is active, the turbo VAD decision being based on the spectral VAD decisions and a power-based decision indicating whether an estimated instantaneous power level of a frame including data packets is greater than a power threshold, and a finite state machine (FSM) unit configured to select which of the input streams to output as an active stream based on a plurality of the turbo VAD decisions, the turbo VAD decision being based in part on feedback provided by the FSM. | 03-28-2013 |
20130077549 | INTEGRATED CIRCUIT AND METHOD WITH PRE-BEACON ACTIVATION TIME ADJUSTMENT - An integrated circuit including a transceiver module that receives beacons from an access point (AP), and transition a wireless network device to an active mode based on: a predetermined beacon interval; and a first predetermined period prior to one of multiple beacons. A timestamp module calculates a first correction value based on a first timestamp received from the AP. An adjustment module adjusts the first predetermined period based on the first correction value. A beacon module detects a beacon missed during an inactive mode by the transceiver module. The timestamp module transmits a probe request signal to the AP a second predetermined period after detection of the missed beacon, receives a second timestamp from the AP in response to the probe request signal, and recalculates the first correction value based on the second timestamp. The adjustment module adjusts the first predetermined period based on the recalculated first correction value. | 03-28-2013 |
20130080664 | SYSTEMS AND METHODS FOR CREATING BIDIRECTIONAL COMMUNICATION CHANNELS USING BLOCK DEVICES - A system includes an initiator device including an initiator interface. A target device includes a target interface that communicates with the initiator interface via a protocol. The protocol supports commands being sent from the initiator device to the target device. The protocol does not support commands being sent from the target device to the initiator device. The target interface is configured to send a command to the initiator device via the protocol. The initiator interface is configured to execute the command. | 03-28-2013 |
20130080666 | HARD DISK DRIVE INTEGRATED CIRCUIT WITH INTEGRATED GIGABIT ETHERNET INTERFACE MODULE - An integrated circuit of a hard disk drive includes an Ethernet network interface module configured to transmit and receive data packets via an Ethernet connection. The data packets respectively include packet headers and at least one of small computer system interface (SCSI) commands and SCSI data requests. A processor is configured to process the data packets transmitted and received by the Ethernet network interface module. A hard disk control module is configured to control, based on the at least one of the SCSI commands and the SCSI data requests, writing of data to a hard disk and reading of the data from the hard disk. Each of the hard disk control module, the processor, and the network interface module is located in the integrated circuit. | 03-28-2013 |
20130080729 | PILOT PLACEMENT FOR NON-VOLATILE MEMORY - A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison. | 03-28-2013 |
20130082359 | REMOVING CONDUCTIVE MATERIAL TO FORM CONDUCTIVE FEATURES IN A SUBSTRATE - Apparatuses having, and methods for forming, conductive features are described. A hole is formed in a substrate and a conductive material is deposited in the hole. A part of the conductive material that occupies a first lengthwise portion of the hole is removed, and a conductive feature that occupies a second lengthwise portion of the hole remains in the substrate. | 04-04-2013 |
20130083122 | OPERATING MECHANISM FOR AN INKJET PRINTER - A printer system includes a print head assembly that ejects a printing solution from a fixed position during a print period and a conveying mechanism operable to convey an operations assembly. The operations assembly executes servicing functions on the print head assembly during a non-print period. Furthermore, the print head assembly remains in the fixed position during the non-print period and the operations assembly provides support for a print medium during the print period. | 04-04-2013 |
20130083836 | CONCATENTATION-ASSISTED SYMBOL-LEVEL COMBINING FOR MIMO SYSTEMS WITH HARQ AND/OR REPETITION CODING - Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The receiver combines the received vectors by vector concatenation The concatenated vector may then be decoded using, for example, maximum-likelihood decoding. In some embodiments, the combined signal vector is equalized before decoding. | 04-04-2013 |
20130088727 | POSITIONAL DATA ERROR CORRECTION - Systems, apparatuses, and methods for correcting systematic errors in positional data of electronic devices configured to navigate across a surface. An apparatus configured to correct positional errors may comprise one or more navigation sensors, and a position module configured to control the one or more navigation sensors to capture a plurality of navigational measurements and adjust the navigational measurements by one or more scaling factors to determine a translation path of the apparatus over a medium. The one or more scaling factors may be constructed by capturing a plurality of navigational measurements to determine a detected translation path of an apparatus, comparing an actual translation path of the apparatus to the detected translation path of the apparatus, and generating the one or more scaling factors based at least in part on a difference between the actual translation path and the detected translation path. Other embodiments also are described. | 04-11-2013 |
20130088965 | BUFFER MANAGER AND METHODS FOR MANAGING MEMORY - Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed. | 04-11-2013 |
20130091307 | METHOD AND APPARATUS FOR EFFECTIVELY INCREASING A COMMAND QUEUE LENGTH FOR ACCESSING STORAGE - The present disclosure includes systems and techniques relating to effectively increasing a command queue length for accessing storage, such as by increasing the Queuing Depth (Q-Depth) of Native Command Queuing (NCQ) Commands. In some implementations, a method can comprise receiving a first command to access a first memory location of a storage device; receiving a second command to access a second memory location of a storage device; constructing a consolidated command including a memory address and a data transfer count associated with each of the first command and the second command; constructing an information command having consolidation information about the consolidated command; and communicating the information command and the consolidated command to the storage device for processing by the storage device. | 04-11-2013 |
20130091579 | INTELLIGENT CONNECTORS INTEGRATING MAGNETIC MODULAR JACKS AND INTELLIGENT PHYSICAL LAYER DEVICES - An apparatus comprises a connector, wherein the connector comprises i) a jack, wherein the jack comprises a) a plurality of electrical terminals, and b) a magnetic component electrically coupled to the plurality of electrical terminals; and ii) a physical layer device, wherein the physical layer device comprises a) a physical layer module, wherein the physical layer module comprises an interface configured to receive packets from the jack, and an interface bus configured to inspect the packets, and b) a network interface configured to, based on the inspection of the packets by the interface bus, provide the packets to a device separate from the physical layer device. | 04-11-2013 |
20130093568 | ANTENNA INTERFACE FOR RADIO FREQUENCY IDENTIFICATION CIRCUIT - Systems, methods, and other embodiments associated with radio frequency identification (RFID) circuits are described. According to one embodiment, a radio frequency identification circuit includes an antenna network, including an antenna and an antenna interface coupled to the antenna, wherein the antenna interface includes first and second capacitors, which are coupled in series with the antenna. An integrated circuit includes a first pin and a second pin coupled respectively to a first node and a second node of the second capacitor and configured to operate as a reader and a tag in combination with the antenna network, and an amplifier embedded in the integrated circuit and configured to provide an output admittance determined by a ratio of current and voltage negative feedback signals such that a frequency response of the combined integrated circuit and antenna network is adjustable without increasing power consumption of the RFID when operating as a reader. | 04-18-2013 |
20130094390 | LOCATION AWARE BACKGROUND ACCESS POINT SCANNING FOR WLAN - Respective distances between a communication device and a plurality of wireless local area network (WLAN) access points are determined. One of the plurality of WLAN access points with which the communication device is to associate is selected based on the determined distances. | 04-18-2013 |
20130094973 | SYSTEMS AND METHODS FOR PROGRAMMING OF A COOLING FAN ARRANGEMENT - Embodiments of the present disclosure provide a method that comprises, based upon receipt of a mode command, changing an operating mode of a fan motor controller of a fan to a serial port communication protocol, programming a memory of the fan motor controller with an operating parameter of the fan, and based upon receipt of a serial port command, changing the operating mode of the fan motor controller from the serial port communication protocol to another protocol. | 04-18-2013 |
20130097344 | Circuit with memory and support for host accesses of storage drive memory - A circuit including a first memory and a processor. The processor is configured to receive data from a host device and transfer the data from the circuit to a storage drive. The processor is configured to receive the data back from the storage drive when a second memory in the storage drive does not have available space for the data, and prior to the data being transferred from the second memory to a third memory in the storage drive. The processor is configured to: store the data received from the storage drive in the first memory or transfer the data received from the storage drive back to the host device; and based on a request received from the storage drive, transfer the data from the first memory or the host device back to the storage drive. The request indicates that space is available in the second memory for the data. | 04-18-2013 |
20130099865 | LOW-STRESS CASCODE STRUCTURE - An amplifier system comprises a cascode common-source (CS) amplifier including a plurality of transistors connected in a common-source configuration. A stress reducing circuit is connected to at least one of the plurality of transistors to equalize a voltage drop across the plurality of transistors. The stress reducing circuit includes a first transistor including a control terminal, a first terminal and a second terminal. The second terminal of the first transistor is connected to a first terminal of a first one of the plurality of transistors. A capacitance has a first terminal connected to the control terminal of the first transistor and a second terminal connected to a control terminal of a second one of the plurality of transistors. | 04-25-2013 |
20130101060 | SYSTEMS AND METHODS FOR SUPPRESSING INTERFERENCE IN A WIRELESS COMMUNICATION SYSTEM - Systems and methods are provided for suppressing interference from a received data signal. A characteristic of a channel is estimated, the channel being configured for transmission of data between a transmitting device and a receiving device having two or more receive antennas. A spatial correlation of interference is determined for the two or more receive antennas based on the channel characteristic. The received data signal is filtered based on the spatial correlation. | 04-25-2013 |
20130102256 | SYSTEMS AND METHODS FOR SUPPRESSING INTERFERENCE IN A SIGNAL RECEIVED BY A DEVICE HAVING TWO OR MORE ANTENNAS - Systems and methods for suppressing interference from a data signal received at a receiving device, where the receiving device has two or more receive antennas, are provided. Characteristics of a channel are estimated, the channel being a channel through which the data signal was transmitted by a transmitting device to the receiving device. A spatial correlation of interference and noise received at the two or more receive antennas of the receiving device is determined based on the estimated characteristics of the channel. The spatial correlation indicates how the interference and noise received at a particular one of the receive antennas is related to the interference and noise received at another one of the receive antennas. The spatial correlation of the interference and noise is used to suppress interference and noise from the data signal received at the receiving device. | 04-25-2013 |
20130103899 | SYSTEM ON CHIP WITH RECONFIGURABLE SRAM - A system on chip includes electrical components and a first memory including memory blocks. A method of operating the system on chip includes generating an assignment of the memory blocks to the electrical components. The generating includes, initially, during a development phase of the system on chip, generating the assignment so that selected memory blocks of the memory blocks are assigned to first selected electrical components of the electrical components as emulated read-only memory. The generating includes, subsequently, during an operational phase of the system on chip, modifying the assignment so that one or more of the selected memory blocks are re-assigned to second selected electrical components of the electrical components as cache memory. The method also includes, according to the assignment, dynamically creating electrical connectivity between the memory blocks and the electrical components. | 04-25-2013 |
20130113451 | INTELLIGENT SWITCHING CONTROLLER AND POWER CONVERSION CIRCUITS AND METHODS - A power conversion circuit comprising a voltage estimation circuit, a current estimation circuit, and a pulse width modulation circuit. The voltage estimation circuit is configured to receive a voltage corresponding to an input of an inductor of the power conversion circuit and generate an estimate of an output voltage of the power conversion circuit based on the voltage. The current estimation circuit is configured to receive a current corresponding to a switch connected in series with the inductor and generate an estimate of an output current of the power conversion circuit based on the current. The pulse width modulation circuit is configured to produce a pulse width modulated signal based on the estimate of the output voltage and the estimate of the output current. | 05-09-2013 |
20130113568 | PUSH-PULL LOW-NOISE AMPLIFIER WITH AREA-EFFICIENT IMPLEMENTATION - An amplifier integrated circuit (IC) includes a push-pull configuration including a push stage and a pull stage. A first loop of wire is configured to form a first degeneration inductance of the push stage. A second loop of wire is configured to form a first degeneration inductance of the pull stage. The first and second loops are concentric. | 05-09-2013 |
20130113645 | DETECTION AND ESTIMATION OF RADIO FREQUENCY VARIATIONS - A system including a sampling module that generates samples of RF signals on a first channel during first, second, and third periods, which do not overlap. A difference module determines a first difference between i) a first count of polarity reversals during the first period and ii) a second count of polarity reversals during the second period; a second difference between i) the second count and ii) a third count of polarity reversals during the third period; and a third difference between the first and second differences. A third module determines a frequency of the RF signals based on at least one of the first and second counts, determines a frequency variation of the RF signals based on the first and second counts, and identifies a radar type of the RF signals based on at least one of the third difference and the frequency variation. | 05-09-2013 |
20130114452 | NETWORK ACCESS MECHANISM BASED ON POWER - Systems and methods for accessing a contention-based communications network are provided. In systems and methods for accessing a contention-based communications network, an access point in the network is created. The access point is a first node connected to the network configured to receive a request from a second node to gain access to the network. A power of a signal transmitted between the access point and the second node is measured. A probability that the second node will access the network is determined based on the measured power of the signal transmitted between the access point and the second node. A determination of whether to permit the second node to gain access to the network is made based on the determined probability. | 05-09-2013 |
20130114654 | PRECODING FEEDBACK FOR CROSS-POLARIZED ANTENNAS WITH MAGNITUDE INFORMATION - A method includes receiving in a mobile communication terminal a precoded Multiple-Input Multiple-Output (MIMO) signal, which includes first and second signal components transmitted at respective different first and second polarizations. A difference between respective signal magnitudes of the first and second signal components received in the terminal is estimated in the terminal. Feedback information, which includes at least an indication of the difference between the signal magnitudes, is calculated and transmitted from the terminal. | 05-09-2013 |
20130114655 | CODEBOOK SUB-SAMPLING FOR FREQUENCY-SELECTIVE PRECODING FEEDBACK - A method includes, in a mobile communication terminal, holding a definition of a sub-sampled codebook identifying precoding matrices, which are selected from a master codebook that is made-up of a wideband codebook and a frequency-selective codebook. The definition defines a first subset of the wideband codebook and a second subset of the frequency-selective codebook. The second subset of the frequency-selective codebook is represented using no more than two bits. A Multiple-Input Multiple-Output (MIMO) signal is received in the terminal. Based on the received MIMO signal, one or more precoding matrices are selected from the sub-sampled codebook for precoding subsequent MIMO signals transmitted to the terminal, and precoding feedback indicating the selected precoding matrices is calculated. The precoding feedback is transmitted from the terminal. | 05-09-2013 |
20130114764 | Physical Layer Frame Format Design for Wideband Wireless Communications Systems - Systems and methods are provided for processing a payload portion of a received signal in a single carrier mode or a multiple carrier mode using a wireless channel receiver based on a portion of the received signal, where a signaling portion of the received signal is a single carrier signal. A single carrier signaling portion is received, and whether the payload portion of the signal is a single carrier signal or a multiple carrier signal is detected from the received single carrier signaling portion. The payload portion of the received signal is demodulated in a single carrier mode if the detecting determines that the payload portion of the received signal is a single carrier signal, and the payload portion of the received signal is demodulated in a multiple carrier mode if the detecting determines that the payload portion of the received signal is a multiple carrier signal. Data from the demodulated payload portion of the received signal is stored in a computer-readable memory. | 05-09-2013 |
20130115988 | METHODS AND APPARATUS FOR MITIGATING KNOWN INTERFERENCE - Systems and methods for mitigating known interference at a receiving device are provided. A signal from a transmission source is received by a receiving device that is affected by an interference source. At least one of a first pilot signal associated with the transmission source and a second pilot signal associated with the interfering source is determined. The first pilot signal includes information broadcast from the transmission source and the second pilot signal includes information broadcast from the interference source. Interference caused by the interference source is mitigated from the received signal using at least one of the first pilot signal and the second pilot signal. | 05-09-2013 |
20130117408 | Method and Apparatus for Arbitration of Time-Sensitive Data Transmissions - The present disclosure describes techniques and apparatuses for arbitration of time-sensitive data transmissions. In some aspects a start of the first scheduled data transmission may be advanced effective to increase the duration of time between an end of the first scheduled data transmission and a start of a second scheduled data transmission. A non-scheduled data transmission can then be performed during the increased duration of time between the end of the advanced first scheduled data transmission and the start of the second scheduled data transmission. | 05-09-2013 |
20130117637 | ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS - Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells. | 05-09-2013 |
20130121089 | SYSTEMS AND METHODS FOR REDUCING PEAK POWER CONSUMPTION IN A SOLID STATE DRIVE CONTROLLER - In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power consumption in a device. The first signal is combined with the second signal to generate a combined signal, and at least a portion of the second signal is shifted in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal. | 05-16-2013 |
20130121348 | Frequency Duplication Mode for Use in Wireless Local Area Networks (WLANs) - In generating a physical layer (PHY) frequency duplication mode data unit for transmission via a communication channel, a preamble of the PHY frequency duplication mode data unit is generated. The preamble includes a signal field, and the preamble is configured so that a receiver can determine that the data unit is a frequency duplication mode-type data unit prior to decoding the signal field of the preamble. A payload of the PHY frequency duplication mode data unit is generated, and the PHY frequency duplication mode data unit is transmitted. | 05-16-2013 |
20130121393 | CHANNEL ESTIMATION WITH DECISION FEEDBACK - Systems, methods, and other embodiments associated with a method for estimating a channel between a wireless transmitter and a wireless receiver are described. According to one embodiment, a method includes receiving a signal that includes non-pilot data that is not known to a receiver of the signal; determining an estimated channel for the signal based, at least in part, on the non-pilot data; processing the signal based, at least in part, on the estimated channel to produce an equalized signal; and decoding the equalized signal to produce output data. | 05-16-2013 |
20130122953 | DIFFERENTIAL CQI ENCODING FOR COOPERATIVE MULTIPOINT FEEDBACK - A method includes receiving in a mobile communication terminal signals from multiple cells that coordinate transmission of the signals with one another in a Cooperative Multipoint (CoMP) scheme. At least first and second Channel Quality Indicators (CQIs), for respective communication channels over which the signals are received, are calculated in the terminal based on the received signals. The second CQI is differentially encoded relative to the first CQI. Feedback information, including the first CQI and the differentially-encoded second CQI, is transmitted from the terminal. | 05-16-2013 |
20130124844 | Dynamic Boot Image Streaming - The present disclosure describes apparatuses and techniques for dynamic boot image streaming. In some aspects a memory controller that is streaming multiple boot images from a first memory to a second memory is stalled, a descriptor for streaming one of the multiple boot images from the first memory to a non-contiguous memory location is generated while the memory controller is stalled, and the memory controller is resumed effective to cause the memory controller to stream, based on the descriptor generated while the memory controller is stalled, the second boot image to the non-contiguous memory location. | 05-16-2013 |
20130124918 | SELF-REPARABLE SEMICONDUCTOR AND METHOD THEREOF - A semiconductor device includes a plurality of processors and a spare processor configured to perform respective processing functions. A plurality of first switches is located at respective inputs of the plurality of processors. Each of the plurality of first switches is configured to selectively provide an input signal to a respective one of the plurality of processors and the spare processor. A first multiplexer is located at an input of the spare processor. The first multiplexer is configured to receive the input signals from each of the plurality of first switches and route, to the spare processor, a selected one of the input signals corresponding to a failed one of the plurality of processors. The spare processor is further configured to perform a processing function associated with the failed one of the plurality of processors in response to receiving the selected one of the input signals. | 05-16-2013 |
20130127051 | WINDOW BALL GRID ARRAY (BGA) SEMICONDUCTOR PACKAGES - A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate. | 05-23-2013 |
20130127550 | FREQUENCY SCALING OF VARIABLE SPEED SYSTEMS FOR FAST RESPONSE AND POWER REDUCTION - A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers. | 05-23-2013 |
20130128288 | BIT SELECTION FROM PRINT IMAGE IN MEMORY OF HANDHELD IMAGE TRANSLATION DEVICE - Systems, apparatuses, and methods for selecting bits from a defined print image in memory of a handheld imaging translation device are described herein. The bits may be selected by determining a location of a print nozzle, mapping the location to a memory location, and selecting a bit from the memory location. Other embodiments may be described and claimed. | 05-23-2013 |
20130128648 | LAYOUTS FOR MEMORY AND LOGIC CIRCUITS IN A SYSTEM-ON-CHIP - An integrated circuit including a plurality of memory circuits and a plurality of logic circuits. The plurality of memory circuits is arranged on a die along a plurality of rows and a plurality of columns. Each memory circuit includes a plurality of memory cells. The plurality of logic circuits is arranged on the die between the plurality of memory circuits along the plurality of rows and the plurality of columns. The plurality of logic circuits is configured to communicate with one or more of the memory circuits. | 05-23-2013 |
20130128798 | 802.11 RESTRICTED ACCESS WINDOW - A method of operating an access point includes defining a restricted access window during which stations that belong to a same infrastructure basic service set as the access point are not allowed to transmit data frames. The method further includes generating a beacon announcing the restricted access window, and transmitting the beacon to the stations that belong to the same infrastructure basic service set as the access point. The method also includes, during the restricted access window, receiving a poll frame from a first station of the stations that belong to the same infrastructure basic service set as the access point. The method further includes, subsequent to the poll frame, transmitting a data frame to the first station. | 05-23-2013 |
20130128885 | DATA PATH ACCELERATION USING HW VIRTUALIZATION - A processing core includes a packet classifier, implemented in a single processing core, configured to classify incoming data packets into first data packets of a known data packet flow and into second data packets of an unknown data packet flow, a first path thread, implemented in the single processing core, configured to process ones of the first data packets at least by forwarding the first data packets to a destination that corresponds to a previously determined destination associated with the known data packet flow, and a second path thread, implemented in the single processing core, configured to process a received second data packet at least to determine a new data packet flow for the second data packet. | 05-23-2013 |
20130132799 | PROVIDING LOW-LATENCY ERROR CORRECTING CODE CAPABILITY FOR MEMORY - A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length. | 05-23-2013 |
20130136063 | PHY Preamble Format For Wireless Communication System - A system and method of extracting data from data packets transmitted over a wireless network includes receiving a data packet having a preamble portion and a payload portion. The preamble portion is cross correlated with a first known spreading sequence to generate a first timing signal and the preamble portion is cross correlated with a second known spreading signal to generate a frame timing signal. An impulse is detected in the first timing signal and a first timing parameter is set based upon the detected impulse in the first timing signal. An impulse is detected in the frame timing signal and a frame timing parameter is set based upon the detected impulse in the frame timing signal. Data is extracted from the received payload portion according to the first timing parameter and the frame timing parameter. | 05-30-2013 |
20130138881 | Parallel Reed-Solomon RAID (RS-RAID) Architecture, Device, and Method - The parallel RS-RAID data storage architecture can aggregate that data and checksums within each cluster into intermediate or partial sums that are transferred or distributed to other clusters. The use of intermediate data symbols, intermediate checksum symbols, cluster configuration information on the assignment of data storage devices to clusters and the operational status of data storage devices, and the like, can reduce the computational burden and latency for the error correction calculations while increasing the scalability and throughput of the parallel RS-RAID distributed data storage architecture. | 05-30-2013 |
20130143366 | ALPHA SHIELDING TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect layer, a first shielding structure disposed in the electrically insulative layer and electrically coupled to the pad structure, an under-ball metallization (UBM) structure electrically coupled to the first shielding structure, and a solder bump electrically coupled to the UBM structure, the solder bump comprising a solder bump material capable of emitting alpha particles, wherein the first shielding structure is positioned between the solder bump and the plurality of integrated circuit devices to shield the plurality of integrated circuit devices from the alpha particles. Other embodiments may be described and/or claimed. | 06-06-2013 |
20130147025 | METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP - A first chip is mounted on a substrate and includes a plurality of bump pads located on an active surface of the first chip. A wire bonds a first bump pad to the substrate. An intermediate layer is disposed on a portion of the active surface of the first chip, and a via within the intermediate layer extends to a second bump pad. A second chip is disposed on the intermediate layer, and wherein the second chip includes a third bump pad located on an active surface of the second chip and aligned with the via formed in the intermediate layer. A corresponding bump is disposed on one or more of the second bump pad and the third bump pad, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. | 06-13-2013 |
20130147423 | METHOD AND APPARATUS FOR POWER SWITCHING - Aspects of the disclosure provide a circuit. The circuit includes a switch and a switch controller. The switch is between a first node that receives a first power supply and a second node, and is controlled to couple/decouple the second node with the first node to switch on/off a second power supply at the second node. The switch controller is configured to generate a switch control signal to control a charging current flowing through the switch to switch on the second power supply. | 06-13-2013 |
20130148755 | PRECODING CODEBOOKS FOR MIMO COMMUNICATION SYSTEMS - A method for communication includes configuring a communication system that includes a transmitter and a receiver with first precoding matrices for mapping up to N data streams onto N transmit antenna ports of the transmitter. Each of at least some of the first precoding matrices are derived from respective second and third precoding matrices. The second and third precoding matrices are configured for mapping data onto respective numbers of transmit antenna ports that are less than N. The data streams are mapped onto the N transmit antenna ports using a precoding scheme based on one of the first precoding matrices. The mapped data streams are transmitted over the N transmit antenna ports from the transmitter to the receiver. | 06-13-2013 |
20130151920 | METHOD AND APPARATUS FOR DECODING - Aspects of the disclosure can provide a method and an apparatus to decode a data stream based on multiple transmissions with efficient usages of storage and power resources. The method can include receiving a first plurality of encoded code blocks corresponding to a first transmission of a transport block, decoding the first plurality of encoded code blocks into decoded code blocks, error detecting the decoded code blocks, and storing a decoding history of the decoded code blocks. Further, the method can include receiving a second plurality of encoded code blocks corresponding to a retransmission of the transport block. The second plurality of encoded code blocks can map the first plurality of encoded code blocks, respectively. The method can selectively decode a subset of the second plurality of encoded code blocks based on the decoding history. In addition, the method can include storing soft bits for code blocks that failed decoding. | 06-13-2013 |
20130154510 | CURRENT BALANCING CIRCUITS FOR LIGHT-EMITTING-DIODE-BASED ILLUMINATION SYSTEMS - A system including a first transistor, a second transistor, and a comparator. The first transistor is configured to supply a first current to a first load connected to a first terminal of the first transistor. The second transistor is configured to supply a second current to a second load connected to a first terminal of the second transistor, wherein the first current and the second current have a predetermined ratio. The comparator is configured to compare a voltage at the first terminal of the first transistor or a voltage at the first terminal of the second transistor to a reference voltage, and to adjust, based on the comparison, biasing of the first transistor and the second transistor to maintain the predetermined ratio between the first current and the second current. | 06-20-2013 |
20130154615 | RF POWER DETECTION CIRCUIT WITH INSENSITIVITY TO PROCESS, TEMPERATURE AND LOAD IMPEDANCE VARIATION - A circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance. | 06-20-2013 |
20130154881 | POWER AMPLIFIER ADJUSTMENT FOR TRANSMIT BEAMFORMING IN MULTI-ANTENNA WIRELESS SYSTEMS - One or more beamsteering matrices are applied to one or more signals to be transmitted via multiple antennas. After the one or more beamsteering matrices are applied to the one or more signals, the plurality of signals is provided to a plurality of power amplifiers coupled to the multiple antennas. Signal energies are determined for the plurality of signals provided to the plurality of power amplifiers, and relative signal energies are determined based on the determined signal energies. Output power levels of the plurality of power amplifiers are adjusted based on the determined relative signal energies. | 06-20-2013 |
20130155167 | LASER OSCILLATING MIRROR SUPPORT FOR COLOR PRINTER - Systems, apparatuses, and methods for pre-rendering image data for a plurality of scanning paths are described here. The method includes receiving image data including a plurality of scan lines for a top portion of an image page, pre-rendering the data for a first scanning path to generate a first data set, pre-rendering the data for a second scanning path to generate a second data set, determining an initial scanning direction, and selecting the first data set or the second data set responsive to said determining. Other embodiments may be described and claimed. | 06-20-2013 |
20130155776 | INTER-CELL INTERFERENCE CANCELLATION - A method includes selecting a first memory cell located along a first bit line and a first word line of a memory array. The method further includes selecting a second memory cell located along (i) the first word line, (ii) a second word line that is adjacent to the first word line, or (iii) a second bit line that is adjacent to the first bit line. A location of the second memory cell is selected based on a predetermined sequence of programming the memory cells. The method further includes writing data in the first memory cell, subsequently writing data in the second memory cell, and reading the first memory cell and the second memory cell. The method further includes detecting one or more states of the second memory causing interference to the first memory cell. | 06-20-2013 |
20130156001 | REFERENCE SIGNAL DESIGN FOR COORDINATED MULTIPOINT TRANSMISSION - A method includes controlling a set of transmission points, which are configured to operate in accordance with a Coordinated Multipoint (CoMP) transmission scheme, to simultaneously transmit a composite Reference Signal (RS) to a mobile communication terminal. Feedback, which is indicative of a response of a composite communication channel between the transmission points and the terminal, is received from the terminal. The feedback is estimated in the terminal based on the composite RS received in the terminal from the transmission points. Subsequent transmission from the transmission points is configured based on the received feedback. | 06-20-2013 |
20130156123 | EFFICIENT MIMO TRANSMISSION SCHEMES - A method for communication includes, in a transmitter having a first number of transmit antenna ports, setting an upper limit on a second number of spatial layers to be used by the transmitter to be less than the first number. An actual number of the spatial layers, which does not exceed the upper limit, is allocated for transmission to a given receiver. One or more streams of modulated symbols are mapped onto the allocated actual number of the spatial layers. The actual number of the spatial layers are transmitted from the transmitter to the given receiver. | 06-20-2013 |
20130157565 | METHOD AND APPARATUS FOR CHARGING A BATTERY IN A MOBILE DEVICE THROUGH A NEAR FIELD COMMUNICATION (NFC) ANTENNA - A near field communication (NFC) antenna in a mobile device is used to wirelessly charge a battery in the mobile device by placing the mobile device on, or in very close proximity to, a charging station that emits an electromagnetic field. An induced current from the NFC antenna is detected that is above a predetermined threshold for longer than a predetermined duration. The induced current is used to charge the battery in the mobile device. | 06-20-2013 |
20130159595 | Serial Interface for FPGA Prototyping - In aspects of serial interface for FPGA prototyping, an advanced crossbar interconnect (AXI) bridge structure enables serial data communication between field programmable gate arrays (FPGA) in a system-on-chip (SoC). The AXI bridge structure includes a parallel interface configured to receive AXI data signals from an AXI component implemented at a first FPGA. A transmit (TX) engine is configured to packetize the AXI data signals into an AXI data packet, and transmit the AXI data packet to a second FPGA via a serial link. The AXI bridge structure also includes a receive (RX) engine configured to receive an additional AXI data packet from the second FPGA via the serial link, and extract AXI data signals from the additional AXI data packet. The parallel interface is further configured to provide the additional AXI data signals to the AXI component. | 06-20-2013 |
20130162156 | METHOD AND APPARATUS FOR CURRENT CONTROL WITH LED DRIVER - Aspects of the disclosure provide a circuit that includes a detection circuit and a controller. The detection circuit is configured to detect a starting of a conduction in a power supply provided via an electronic transformer. The controller is configured to control a current regulating circuit to pull a current from the electronic transformer at a pre-determined level during a time duration following the starting of the conduction, and pull the current at a reduced level according to a pre-determined profile after the time duration. | 06-27-2013 |
20130163604 | METHOD AND APPARATUS FOR FLEXIBLE INTERFACE BYPASS OPTIONS IN SWITCHES - A network apparatus including a central processing unit, first physical layer devices, a second physical layer device, and a network switch. The network switch includes first ports communicating with the first physical layer devices; a second port communicating with the second physical layer device; and third and fourth ports communicating with the central processing unit over first and second media independent interfaces, respectively. The network switch includes a switch core module configured to route data packets between connected ports, including the first and third ports. The network switch includes a bypass switch configured to (i) in response to a first mode being selected, directly connect the second port and the fourth port, bypassing the switch core module, and (ii) in response to a second mode being selected, disconnect the second port from the fourth port and connect the second and fourth ports to the switch core module. | 06-27-2013 |
20130163657 | OPTIMAL LINEAR EQUALIZER FOR MIMO SYSTEMS WITH HARQ AND/OR REPETITION CODING - Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors based on the same transmitted vector. The symbols of the received signal vectors are combined, forming a combined received signal vector that may be treated as a single received signal vector. The combined received signal vector may be equalized by, for example, a zero-forcing or minimum-mean-squared error equalizer or another suitable linear equalizer. Following equalization, the equalized signal vector may be decoded using a simple, linear decoder. | 06-27-2013 |
20130165055 | OUTPUT STAGE FOR WIRELESS TRANSMITTER - In one embodiment, an apparatus includes a first block configured to decompose an input signal into a positive component and a negative component. The apparatus further includes a second block configured to generate a mixer positive driver component from the positive component and a mixer negative driver component from the negative component and input the mixer positive driver component and the negative driver component into a mixer for a wireless transmitter. | 06-27-2013 |
20130171775 | EXPOSED DIE PAD PACKAGE WITH POWER RING - A method of fabricating a packaged semiconductor includes forming a conductive frame as an integral piece of conductive material. The frame includes an inner portion and a ring portion encircling the inner portion. The ring portion includes a first ring portion encircling first and second sides of the inner portion, and a first bar portion located on a third side of the inner portion. The method includes mounting a semiconductor die to a first surface of the inner portion of the frame. The die is configured to receive power via the first ring portion. The method includes applying a casing, which covers the die, to the frame. The method includes, after the casing is applied to the frame, removing (i) sections of the frame that connect the inner portion to the ring portion, and (ii) sections of the frame that connect the first ring portion to the first bar portion. | 07-04-2013 |
20130173776 | Method and Apparatus for Wirelessly Managing a Classroom Environment - This disclosure describes devices, methods, and techniques for managing a classroom environment. These devices, method, and/or techniques enable a classroom manager device to manage a wireless classroom environment. | 07-04-2013 |
20130173950 | METHOD AND APPARATUS FOR COMMUNICATING TIME INFORMATION BETWEEN TIME AWARE DEVICES - According to one embodiment, an apparatus includes a first processing unit operating according to a first clock, a second processing unit operating according to a second clock running separately from the first clock, and a synchronization controller coupled to the first communication unit and the second communication unit. The synchronization controller is configured to (i) cause the first communication unit to generate a first indication of time at which the first processing unit transmits a signal to the second processing unit, according to the first clock, (ii) cause the second processing unit to generate a second indication of time at which the second processing unit receives the signal, according to the second clock, and (iii) determine an offset between the first clock and the second clock based on the first indication of time and the second indication of time. | 07-04-2013 |
20130173990 | HIGH-THROUGHPUT ITERATIVE DECODING'S DEFECT SCAN IN RETRY MODE OF STORAGE SYSTEM CHANNEL - The present disclosure includes systems and techniques relating to decoding signals produced within a storage device. A described technique includes retrieving a first codeword from a storage medium, decoding the first codeword, performing a retry process when the decoding was not successful, and retrieving one or more second codewords from the storage medium during the retry process to at least maintain a drive throughput. The retry process can include identifying one or more data chunks within the first codeword having potential defects, generating an erasure mask based on the one or more data chunks, applying, based on a window, one or more erasures within one or more different regions of the first codeword based on one or more corresponding regions of the erasure mask to produce one or more versions of the first codeword, and decoding the one or more versions of the first codeword. | 07-04-2013 |
20130173995 | METHOD AND APPARATUS FOR READING A DISC - Aspects of the disclosure provide a circuit that includes a decoder, an error checking module, and a controller. The decoder is configured to receive codewords, and decode the codewords based on an error correcting code. The error checking module is configured to error-check sectors using an error detecting code in the sectors. Each sector is formed of a plurality of decoded codewords. The controller is configured to store in a memory, when the error checking fails for at least one sector, the decoded codewords and corresponding flags indicative of pass or fail of the decoding of the codewords. | 07-04-2013 |
20130176903 | Methods and Apparatus for Establishing a Tunneled Direct Link Setup (TDLS) Session Between Devices in a Wireless Network - The present disclosure describes techniques for establishing and reestablishing tunneled direct link setup (TDLS) sessions. In some aspects a TDLS persistent capable bit is stored at a computing device to indicate whether the computing device is capable of storing persistent group[ information associated with TDLS sessions. Persistent group information is also stored at the computing device to assist the computing device in reestablishing TDLS sessions and directing reestablishment of TDLS sessions. | 07-11-2013 |
20130177004 | INFORMATION BIT PADDING SCHEMES FOR WLAN - In a method for generating a data unit, a signal field is generated to include a first subfield having one of: a length indication to indicate a number of bytes in a data portion of the data unit, or a duration indication to indicate a number of OFDM symbols in the data portion of the data unit and a second subfield to indicate whether the first subfield includes the length indication or the duration indication. When the first subfield includes the length indication, one or more padding bits are added to a set of information bits according to a first padding scheme. When the first subfield includes the duration indication, one or more padding bits are added to the set of information bits to according to a second padding scheme. Padded information bits are encoded, and the data unit is generated to included the encoded information bits. | 07-11-2013 |
20130177051 | CALIBRATION CORRECTION FOR IMPLICIT BEAMFORMING IN A WIRELESS MIMO COMMUNICATION SYSTEM - A transmitter beamforming technique for use in a MIMO wireless communication system determines a partial description of a reverse channel without determining a full dimensional description of the reverse channel. A correction matrix is developed from the partial description of the reverse channel and a description of the forward channel. The correction matrix is used to process signals to be transmitted via the forward channel, and a steering matrix is used to perform beamforming in the forward channel. | 07-11-2013 |
20130182491 | SYSTEM AND METHOD FOR MODIFYING ACTIVATION OF A SENSE AMPLIFIER - Systems, methods, and other embodiments associated with controlling a sense amplifier in a memory device are described. According to one embodiment, an apparatus includes a signal generator configured to generate a sense enable signal that activates a sense amplifier of a memory cell in a memory device. The apparatus includes a dummy memory cell connected to a current mirror circuit that is configured to detect a timing variation in the dummy memory cell from a predefined timing and to alter a timing of the sense enable signal based, at least in part, on the timing variation. The apparatus also includes a controller configured to modify the timing of the sense enable signal by selectively enabling one or more of a plurality of semiconductor gates in the current mirror circuit. The plurality of semiconductor gates are connected in parallel. | 07-18-2013 |
20130182593 | DATA UNIT FORMAT FOR SINGLE USER BEAMFORMING IN LONG -RANGE WIRELESS LOCAL AREA NETWORKS (WLANS) - A method includes receiving data units each having a preamble with first and second preamble portions, detecting symbol constellation rotations of OFDM symbols in the first preamble portions, and determining, based on the detected rotations, whether the preambles conform to a first format. The method also includes, when it is determined that a preamble conforms to the first format, processing the second preamble portion according to the first format, and, when it is determined that a preamble does not conform to the first format, (i) determining whether information bits in the first preamble portion indicate a single- or multi-user data unit, (ii) when it is determined that the information bits indicate a single-user data unit, processing the second preamble portion according to a second format, and (iii) when it is determined that the information bits indicate a multi-user data unit, processing the second preamble portion according to a third format. | 07-18-2013 |
20130182662 | DATA UNIT FORMAT FOR SINGLE USER BEAMFORMING IN LONG-RANGE WIRELESS LOCAL AREA NETWORKS (WLANS) - A method includes generating a preamble of a first data unit according to a first format. Generating the preamble of the first data unit according to the first format includes generating a first preamble portion of the first data unit and generating a second preamble portion of the first data unit. The first preamble portion of the first data unit includes information indicating to a receiving device that the first data unit is a single-user data unit, and the second preamble portion of the first data unit follows the first preamble portion of the first data unit. The method also includes applying a beamforming steering matrix to the second preamble portion of the first data unit but not to the first preamble portion of the first data unit. | 07-18-2013 |
20130183938 | PERSONAL LIFESTYLE DEVICE - A handheld device including a communication module, a memory, and a search engine. The communication module is configured to, in response to the handheld device being located in a first geographic region, (i) establish communication with a first service provider located in the first geographic region, and (ii) order a service from the first service provider. The memory is configured to store data relating to the order. The search engine is configured to, in response to the handheld device being located in a second geographic region, based on the data relating to the order stored in the memory, search for a second service provider in the second geographic region offering a particular service, where the particular service offered by the second service provide is similar to the service provided by the first service provider. | 07-18-2013 |
20130183954 | INTELLIGENT DETECTION INTERFACE FOR WIRELESS DEVICES - In a method for controlling a wireless device assembly coupled to a host assembly, a clock signal is received at the wireless device assembly from the host assembly. The clock signal is supplied to an interface module in the wireless device assembly during a power save mode of the wireless device assembly and is used to operate the interface module. An initialization command is received at the wireless device assembly from the host assembly and is detected with the interface module. In response to detecting the initialization command, at least a portion of the wireless device assembly, other than the interface module, is activated. | 07-18-2013 |
20130185447 | SYSTEMS AND METHODS FOR ESTABLISHING A WI-FI DISPLAY (WFD) SESSION - Systems, methods, apparatus, and techniques are provided for establishing an application layer communications session over a layer 2 (L2) communications connection. In particular, a discovery request frame is transmitted from a first device. A discovery response frame is received at the first device, where the discovery response frame is transmitted from a second device in response to having received the discovery request frame. An application layer communications session is established between the first device and the second device while maintaining an existing L2 communications connection between the first device and the second device. | 07-18-2013 |
20130188759 | SYSTEMS AND METHODS FOR COMPOSITE ADAPTIVE FILTERING - Systems and methods are provided for adaptively filtering a signal. A signal is received, and the received signal is filtered to generate an output signal. A difference signal is generated based on a difference between the output signal and a reference signal, and a correlation of the received signal and the different signal is evaluated. Then, a mode is selected between a first adaptive filtering mode and a second adaptive filtering mode based at least in part on the correlation, and the received signal is filtered using the selected adaptive filtering mode. | 07-25-2013 |
20130191582 | Cache System Using Solid State Drive - A cache system for a storage device includes (i) one or more solid state drives (SSDs), (ii) one or more random access memories (RAMs), and (iii) a cache control device. The cache control device caches at least some of first data that is to be written to the storage device, and caches at least some of second data that is retrieved from the storage device. When caching first data or second data in one of the one or more RAMs, the cache control device writes to the one RAM non-sequentially with respect to a memory space of the one RAM. When caching first data or second data in one of the one or more SSDs, the cache control device writes to the one SSD sequentially with respect to a memory space of the one SSD. | 07-25-2013 |
20130193572 | BALL GRID ARRAY PACKAGE SUBSTRATE WITH THROUGH HOLES AND METHOD OF FORMING SAME - In accordance with an embodiment, there is provided a substrate of a ball grid array package that includes a first layer including reinforcement fibers. The reinforcement fibers reinforce the first layer such that the first layer has a higher tensile strength relative to a layer in the ball grid array package that is free of reinforcement fibers. In an embodiment, the substrate comprises a second layer disposed adjacent to the first layer with the second layer being free of reinforcement fibers. In an embodiment, the substrate also includes a through hole penetrating each of the first layer and the second layer. The through hole penetrates each of the first layer and the second layer based on each of the first layer and the second layer having been drilled in accordance with a mechanical drilling process. | 08-01-2013 |
20130195001 | MAC Header Compression in Long-Range Wireless Local Area Networks - A method includes receiving, at or from a station STA, a plurality of packets. Each packet includes a set of flag bits, and a MAC header containing at least a first address field specifying a receiver address and a second address field specifying a transmitter address. The method also includes determining whether each set of flag bits indicates that the STA was associated with an AP when the respective packet was generated, and processing the MAC header of each packet. Processing the MAC header of each packet includes processing a third address field in each packet for which it is determined that the respective set of flag bits indicates that the STA was not associated with an AP when the respective packet was generated. The third address field contains a MAC address of the STA. | 08-01-2013 |
20130195085 | METHOD AND APPARATUS FOR DISCOVERING A WIRELESS DEVICE IN A WIRELESS NETWORK - A method for synchronizing the discovery of wireless services or applications in a wireless network using a recurring time interval T in which wireless devices within the wireless network can be in one of a predetermined plurality of time states. The method includes selecting a time state from amongst the plurality of time states, performing discovery by a first wireless device supporting a given service or application once during the recurring time interval T at the selected time state, and repeating the above steps in successive ones of the recurring time interval T until all of the predetermined plurality of time states have been selected. | 08-01-2013 |
20130195092 | SYSTEMS AND METHODS FOR GENERATING PREAMBLE SYMBOLS IN COMMUNICATION SYSTEMS - A method for transmitting an 802.11ah packet is provided. A training field sequence is generated using control circuitry. A preamble for a packet is generated using the control circuitry. The preamble includes a training field symbol which includes the training field sequence. A portion of the training field sequence is within a plurality of guard tones of the training field symbol. The preamble is transmitted using transmit circuitry. | 08-01-2013 |
20130195210 | CHIP-TO-CHIP COMMUNICATIONS - Devices and systems are described for transmitting data packets over a chip-to-chip communications link. For example, a device includes a hardware replay buffer to store a data packet. The data packet includes an overhead portion and a payload portion. Additionally, the transmitter device includes circuitry configured to record a memory location within the hardware replay buffer corresponding to an interruption in transmission to a receiver device of the payload portion of the data packet through a physical serial communications link. The memory location references an intermediate location of the payload portion of the data packet. | 08-01-2013 |
20130198416 | Systems And Methods For Dynamic Priority Control - System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received into the command queue, a command being associated with a priority parameter. A current command first in line to be executed in the command queue is determined, the current command being associated with a first priority parameter. A second command associated with a second priority parameter is determined, the second priority parameter being largest among priority parameters associated with the one or more commands. A final priority parameter for the current command is computed based at least in part on the second priority parameter. | 08-01-2013 |
20130198432 | INTERRUPT HANDLING SYSTEMS AND METHODS FOR PCIE BRIDGES WITH MULTIPLE BUSES - A bridge includes buses, a memory, a component module, an interface and an interrupt module. The component module transfers data between a host control module and a network device via the memory and the buses. The interface is connected between the memory and the network device and transmits status information to the memory via one of the buses. The status information indicates completion of a last data transfer between the network device and the host control module. An interrupt module, subsequent to the status information being transmitted to the memory, detects a first interrupt generated by the network device, and transmits an interrupt message to the component module via the memory and the one of the buses. The component module then generates a second interrupt detectable by the host control module. The second interrupt indicates completion of data transfer between the network device and the host control module. | 08-01-2013 |
20130200933 | FRACTIONAL SPUR REDUCTION USING CONTROLLED CLOCK JITTER - In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL. | 08-08-2013 |
20130201835 | MULTI-CHANNEL WIRELESS COMMUNICATIONS - Systems and techniques relating to wireless communications are described. A described technique includes monitoring wireless communication channels, including a first channel and a second channel, to produce a monitoring output, determining a first transmission period for the first channel by applying a first waiting period duration and a second waiting period duration to the monitoring output, determining a second transmission period for the second channel by applying the first waiting period duration and the second waiting period duration to the monitoring output, causing, based on the first transmission period, a first transmission on the first channel to reserve the group of wireless communication channels; causing, based on the second transmission period, a second transmission on the second channel; and monitoring, after the end of the first transmission period, for an acknowledgement(s), An end of the second transmission period can be aligned with an end of the first transmission period. | 08-08-2013 |
20130202001 | PILOT SEQUENCE DESIGN FOR LONG RANGE WLAN - In a method for generating a physical layer (PHY) data unit, pilot tone contribution sequence values for a first set of orthogonal frequency division multiplexing (OFDM) symbols and for a second set of OFDM symbols are determined using a pilot mapping function. The first set is to be included in a signal field of the data unit, and the second set is to be included in a data portion of the data unit. The first set and the second set are generated to include pilot tones modulated based on the pilot tone contribution sequence values determined, respectively, for the first set of OFDM symbols and for the second set of OFDM symbols. The signal field is generated to include the first set, and the data portion is generated to include the second set. The data unit is generated to include at least the signal field and the data portion. | 08-08-2013 |
20130203413 | METHOD AND APPARATUS FOR DISCOVERING WIRELESS DEVICES - Wireless discovery is the process in which a service or application is located by a wireless station on a network, usually after the station has established a connection with the network. Wireless pre-association refers to the process of describing an application or service by its hardware/software interoperability requirements and/or a unique identifier prior to a connection being established between two or more wireless stations. A method performs wireless discovery between two or more wireless stations by communicating a data string between a wireless station and another wireless station, prior to a connection having been established between the wireless station and another wireless station, the data string including interoperability information necessary for a service or an application to run on a wireless station receiving the data string. | 08-08-2013 |