| Patent application number | Description | Published |
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| 20090013193 | Circuit Building Device - The present invention provides an apparatus for securely acquiring a circuit configuration information set corresponding to a new cryptosystem without increasing the number of reconfigurable circuits. A content playback apparatus | 01-08-2009 |
| 20090055638 | Algorithm update system - A design data storage unit stores a plurality of pieces of design data. A judgment unit | 02-26-2009 |
| 20090067632 | Circuit updating system - An information processing apparatus is provided with a reconfigurable unit ( | 03-12-2009 |
| 20090237113 | SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAM TRANSFORMATION APPARATUS, AND MAPPING APPARATUS - A semiconductor integrated circuit ( | 09-24-2009 |
| 20110126164 | SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAM TRANSFORMATION APPARATUS, AND MAPPING APPARATUS - A mapping apparatus maps, on a semiconductor integrated circuit, a circuit function described in a circuit description, the semiconductor integrated circuit having a plurality of reconfigurable cores arranged separately from one another and having a logic reconfiguration function. A first group of register circuits are formed between at least two reconfigurable cores included in the plurality of reconfigurable cores and temporarily hold an output from one of the reconfigurable cores and transferring the output to another one of the reconfigurable cores. The mapping apparatus includes a divider that divides the circuit function into a plurality of circuit function blocks, an eliminator that eliminates a register from between the plurality of circuit function blocks and a synthesis executer that executes logic synthesis on each of the plurality of circuit function blocks from between which the register has been eliminated. A placing and routing unit places and routes, on each of the reconfigurable cores, each of the plurality of circuit function blocks on which the logic synthesis has been executed. | 05-26-2011 |
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| 20090162936 | Method For Transfer Of Gene Into Fat Cell Or Progenitor Fat Cell - A method for transferring a gene into a fat cell or progenitor fat cell comprising the step of infecting the fat cell or progenitor cell with a retrovirus vector having a foreign gene in the presence of a substance having both of a retrovirus-binding site and a target cell-binding site in the molecule or a mixture of a substance having a retrovirus-binding site and a substance having a target cell-binding site, the target cell-binding site having a region that can bind to VLA-5 and/or a region that can bind to VLA-4. | 06-25-2009 |
| 20100150886 | Method of Producing Lymphocytes - A method for preparing lymphocytes characterized in that the method comprises the step of carrying out expansion in the presence of (a) fibronectin, a fragment thereof or a mixture thereof, (b) a CD3 ligand, and (c) a CD28 ligand. | 06-17-2010 |
| 20110117653 | METHOD FOR PRODUCTION OF PLURIPOTENT STEM CELL - The present invention relates to a method for production of a cell population containing a pluripotent stem cell, said method comprising a step of treating a somatic cell which has been contacted with nuclear reprogramming factors under nutrient-starved condition, and/or a step of treating the somatic cell with an agent capable of arresting cell cycle. The present invention allows induction and growth of pluripotent stem cells at high frequency, and it also allows production of pluripotent stem cells with high efficiency. The nuclear reprogramming factors to be used may be any selected from the group consisting of OCT4, SOX2, c-MYC, KLF4, NANOG and LIN28. | 05-19-2011 |
| Patent application number | Description | Published |
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| 20080272443 | Field effect transistor having field plate electrodes - A field effect transistor includes an active layer formed on a semiconductor substrate, source and drain electrodes formed apart from each other on the active layer, a gate electrode formed between the source and drain electrodes, a first interlayer film formed on the active layer, a first field plate (FP) electrode connected to the gate electrode and provided on the first interlayer film between the gate and drain electrodes, a second interlayer film formed on the first interlayer film, and a second FP electrode connected to the source electrode and provided on the second interlayer film between the first FP and drain electrodes. The field effect transistor is provided which exhibits a comparatively high gain factor at high frequencies. | 11-06-2008 |
| 20080283844 | Method for manufacturing a field effect transistor having a field plate - An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal. | 11-20-2008 |
| 20090001381 | Semiconductor device - A semiconductor device includes a substrate, laminated layers provided on the substrate. The laminated layers include an AlGaN barrier layer as an uppermost layer. A gate electrode is provided in a channel region of the laminated layers. A source electrode and a drain electrode are provided so as to face each other via the channel region interposed therebetween. A silicon nitride film is formed to cover an exposed surface of the laminated layers exposed via the gate electrode, the source electrode and the drain electrode. The silicon nitride film has characteristics that an etching rate thereof is in a range from 1 nm per/min to 2 nm/min for an etchant in which hydrofluoric acid having a concentration of 50 weight percent and ammonium fluoride having a concentration of 40 weight percent are mixed at a mixing ratio of 1:9. | 01-01-2009 |
| 20090242937 | Semiconductor device and manufacturing method - A semiconductor device has source and drain electrodes formed on a substrate, a gate insulation film formed on the substrate between the source and drain electrodes, and a gate electrode formed on the gate insulation film. These elements are all covered by a dielectric sub-insulation film. An opening is formed in the sub-insulation film, partially exposing the gate electrode. A field plate extends from the top of the gate electrode down one side of the gate electrode as far as the sub-insulation film covering the gate insulation film, filling the opening. The thickness of the sub-insulation film can be selected to optimize the separation between the field plate and the substrate for the purpose of reducing current collapse by reducing electric field concentration at the edge of the gate electrode. | 10-01-2009 |
| 20100044752 | Semiconductor device and manufacturing method - A metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) has a substrate in which an electron supply layer is interposed between an electron channel layer and the surface of the substrate. A pair of main electrodes are formed on the surface of the substrate. A recess is formed in the surface of the substrate between the main electrodes. A gate insulation film is formed on the surface of the substrate, at least between the first and second main electrodes, covering the inside walls and floor of the recess. A gate electrode is formed on the gate insulation film, filling in the recess. The gate insulation film has a crystal density of at least 2.9 g/cm | 02-25-2010 |
| 20100258845 | Semiconductor device and method for manufacturing same - There is provided a semiconductor device capable of deactivating 2-dimensional electron gas (2DEG) layers in a buffer layer having a multi-layer film structure. The buffer layer is formed in a high electron mobility transistor (HEMT) formed on a silicon (Si) substrate. The semiconductor device includes the substrate whose uppermost layer is the Si layer, the buffer layer constructed by alternately stacking a plurality of first layers and a plurality of second layers on the Si layer, third layer serving as an electron transit layer formed on the buffer layer, and fourth layer serving as an electron supplying layer formed on the third layer. The first layer is composed of the same material as for the third layer. A p-type impurity is introduced into the first layers so as to deactivate the 2DEG layers formed in the first layer near interfaces between the first and second layers. | 10-14-2010 |
