Patent application number | Description | Published |
20090006895 | Method for debugging reconfigurable architectures - A method is described for debugging reconfigurable hardware. In one example embodiment, debugging information is written for each configuration cycle into a memory which is then evaluated by a debugger. | 01-01-2009 |
20090100286 | METHODS AND DEVICES FOR TREATING AND PROCESSING DATA - A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell. | 04-16-2009 |
20090146690 | RUNTIME CONFIGURABLE ARITHMETIC AND LOGIC CELL - A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers. | 06-11-2009 |
20090146691 | LOGIC CELL ARRAY AND BUS SYSTEM - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 06-11-2009 |
20100023796 | METHODS AND DEVICES FOR TREATING AND PROCESSING DATA - A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell. | 01-28-2010 |
20110010523 | RUNTIME CONFIGURABLE ARITHMETIC AND LOGIC CELL - A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers. | 01-13-2011 |
20120072699 | LOGIC CELL ARRAY AND BUS SYSTEM - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 03-22-2012 |
20120311301 | PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION - In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution. | 12-06-2012 |
20140208143 | Multiprocessor Having Runtime Adjustable Clock and Clock Dependent Power Supply - A multiprocessor that that provides for adjusting the clock frequency for at least some data processing units at runtime and a voltage supply adapted to supply higher supply voltages for data processing at higher clock frequencies. | 07-24-2014 |
20140359254 | Logical cell array and bus system - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 12-04-2014 |
Patent application number | Description | Published |
20090031104 | Low Latency Massive Parallel Data Processing Device - Data processing device comprising a multidimensional array of ALUs, having at least two dimensions where the number of ALUs in the dimension is greater or equal to 2, adapted to process data without register caused latency between at least some of the ALUs in the corresponding array. | 01-29-2009 |
20090144522 | Data Processing Device and Method - A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed. | 06-04-2009 |
20090172351 | DATA PROCESSING DEVICE AND METHOD - A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed. | 07-02-2009 |
20090199167 | Hardware Definition Method - The invention relates to a method for defining hardware, in which a library of parameterizable, executable elements is provided, parameters are selected, the elements comprising selected parameters are compiled, and the compilation is then simplified. | 08-06-2009 |
20100122064 | METHOD FOR INCREASING CONFIGURATION RUNTIME OF TIME-SLICED CONFIGURATIONS - A device may include a data processing logic cell field and one or more sequential CPUs. The logic cell field and the CPUs may be configured to be coupled to each other for data exchange. The data exchange may be in block form using lines leading to a cache memory. In a method for operating a reconfigurable unit having runtime-limited configurations, the configurations may be able to increase their maximum allowed runtime, e.g., by triggering a parallel counter. An increase in configuration runtime by the configurations may be suppressed in response to an interrupt. | 05-13-2010 |
20100241823 | DATA PROCESSING DEVICE AND METHOD - A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed. | 09-23-2010 |
20100281235 | RECONFIGURABLE FLOATING-POINT AND BIT-LEVEL DATA PROCESSING UNIT - Blocks of fixed-point units in a reconfigurable data processing unit assist the efficient calculation of floating decimal point numbers by virtue of joint hardware functions permanently implemented within the block. | 11-04-2010 |
20110119657 | USING FUNCTION CALLS AS COMPILER DIRECTIVES - A method for passing compiler directives into a compiler wherein empty function calls are defined, which call no function, but define compiler directives by its name, is suggested. Thus, by allowing empty functions calls and by handling them automatically, in particular in the automated way suggested, significant improvements over the prior art can be obtained. | 05-19-2011 |
20110173596 | METHOD FOR FACILITATING COMPILATION OF HIGH-LEVEL CODE FOR VARYING ARCHITECTURES - The invention relates to a method for compiling high-level language code for various architectures and/or components. The invention proposes that an architecture-specific precompilation be generated and subsequently the architecture-specific precompilation be compiled taking into account component-specific information. | 07-14-2011 |
20110238948 | METHOD AND DEVICE FOR COUPLING A DATA PROCESSING UNIT AND A DATA PROCESSING ARRAY - The present invention relates to a method of coupling at least one (conventional) unit processing data in a sequential manner, e.g. a CPU, von-Neumann-Processor and/or microcontroller, the (conventional) unit for data processing comprising an instruction pipeline, and an array for processing data comprising a plurality of data processing cells, e.g. a preferably coarse grain and/or preferably runtime reconfigurable data processor, FPGA, DFP, DSP, XPP or chaemeleon-technology-like data processing fabric, wherein the array is coupled to the instruction pipeline. | 09-29-2011 |
20120017066 | LOW LATENCY MASSIVE PARALLEL DATA PROCESSING DEVICE - Data processing device comprising a multidimensional array of ALUs, having at least two dimension where the number of ALUs in the dimension is greater or equal to 2, adapted to process data without register caused latency between at least some of the ALUs in the corresponding array. | 01-19-2012 |
20120137075 | System and Method for a Cache in a Multi-Core Processor - The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data. | 05-31-2012 |
20120216012 | SEQUENTIAL PROCESSOR COMPRISING AN ALU ARRAY - The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle. | 08-23-2012 |
20120278772 | HARDWARE DEFINITION METHOD INCLUDING DETERMINING WHETHER TO IMPLEMENT A FUNCTION AS HARDWARE OR SOFTWARE - A hardware definition system and method includes a computer processor analyzing software function modules of a software program, and generating, for each of at least a subset of the software function modules, and on the basis of the analyzing step, a respective setting indicating whether the respective function module is to be implemented as a respective hardware module or as a software module executed on a hardware module defined in a hardware module library. | 11-01-2012 |
20130024657 | RECONFIGURABLE SEQUENCER STRUCTURE - A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means. | 01-24-2013 |
20130042137 | METHODS AND DEVICES FOR TREATING AND PROCESSING DATA - A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell. | 02-14-2013 |
20130111188 | LOW LATENCY MASSIVE PARALLEL DATA PROCESSING DEVICE | 05-02-2013 |
20130191817 | Optimisation of loops and data flow sections - The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions. | 07-25-2013 |
20130205123 | Data Processing Device and Method - The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles. | 08-08-2013 |
20130339797 | METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES - A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle into a memory, which is then analyzed by the debugger. | 12-19-2013 |
20140052961 | PARALLEL MEMORY SYSTEMS - The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel. | 02-20-2014 |
20140143509 | METHOD AND DEVICE FOR DATA PROCESSING - The present provides a method for operating a module by a processor. The method includes generating, by at least one task being executed on the processor, control information for controlling operation of the module. The module includes an arrangement of a plurality of cells, including a bus system. At least some of the cells having arithmetic and logic units. At least some of the cells being arranged in at least two dimensions. The method further including writing, by the processor, the control information into a memory being shared with the module in a list-like manner to form a list of operations. The method further including executing, by the module, the operations listed in the list. | 05-22-2014 |
20140244973 | RECONFIGURABLE ELEMENTS - The present invention provides for a multiprocessor device on either a chip or a stack of chips. The multiprocessor device includes a plurality of processing entities and a memory system. The multiprocessor device further includes at least one interface unit to at least one of an external memory and one or more peripherals. The multiprocessor device includes a bus system interconnecting the processing entities, the memory system and the at least one interface unit. Wherein, the memory system includes a plurality of cache segments, and the plurality of segments are located on a plurality of memory cores, each having a connection to the bus system. | 08-28-2014 |
20140297914 | CHIP INCLUDING MEMORY ELEMENT STORING HIGHER LEVEL MEMORY DATA ON A PAGE BY PAGE BASIS - A bus system for transferring data between parts of a multiprocessor system. The bus system is divided into a plurality of segments. Each segment is controlled by a table providing routing information. The bus system establishes communication between a sender and a receiver according to data where the data includes an identifier that identifying the source of the data transfer and/or the target of the data transfer. | 10-02-2014 |
20140297948 | METHOD FOR PROCESSING DATA - A method for operating a system on a chip comprising a conventional processor unit (CISC, RISC, VLIW, DSP) and an array processor having a multidimensional arrangement of arithmetic units. Operation information for the array processor are stored in a memory shared between the conventional processor and the array processor. At runtime the conventional processor points the array processor to the memory area comprising the operation information. A management unit inside the array processor is autonomously loading the operation information into the array processor | 10-02-2014 |
20140304449 | Multi-core processor having disabled cores - A multi-core processor having a cache, an interconnect system selectively connecting the cache to individual cores, and a interconnect control whereby selected cores are disabled. | 10-09-2014 |
20140310466 | Multi-processor bus and cache interconnection system - A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method. | 10-16-2014 |
20140310696 | TOOL-LEVEL AND HARDWARE-LEVEL CODE OPTIMIZATION AND RESPECTIVE HARDWARE MODIFICATION - The present invention relates to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block. | 10-16-2014 |
20140331194 | Method for manufacturing a chip from a system definition - A method for manufacturing a chip from a system definition, the system definition describing a plurality of cells, buses and external I/O. The cell definitions are defined by providing two libraries, a first containing a superset of cell definitions; and a second a plurality of HDL definitions of cells selected from the first library. The method further included creating the system definition from the second library, a bus definition, and an external I/O definition. | 11-06-2014 |
20140337601 | CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS - An array processor composed of processor cells that are programmed by a controlling unit, and that are reprogrammed when a cell has finished a current data processing operation, even while other cell continue to process data with their current programming. | 11-13-2014 |
20140351482 | Multi-processor with selectively interconnected memory units - A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units. | 11-27-2014 |
20140351563 | ADVANCED PROCESSOR ARCHITECTURE - The present invention relates to a processor core having an execution unit comprising an arrangement of Arithmetic-Logic-Units, wherein the operation mode of the execution unit is switchable between an asynchronous operation of the Arithmetic-Logic-Units and interconnection between the Arithmetic-Logic-Units such that a signal. from the register file crosses the execution unit and is receipt by the register file in one clock cycle; and wherein a pipelined operation mode of at least one of the Arithmetic-Logic-Units and the interconnection between the Arithmetic-Logic-Units such that a signal requires from the register file through the execution unit back to the register file more than one clock cycles. | 11-27-2014 |
20140359255 | Coarse-Grained Data Processor Having Both Global and Direct Interconnects - A data processor having a plurality of coarse-grained data processing elements arranged in rows and columns, an interconnect structure comprising both global and direct interconnects, the global interconnects interconnecting the coarse-grained data processing elements globally and the direct interconnects interconnecting adjacent data processing elements. | 12-04-2014 |
20150026431 | Method of Processing Data with an Array of Data Processors According to Application ID - A method wherein a plurality of data processors are associated with application IDs whereby the array processes a plurality of applications in parallel. | 01-22-2015 |
20150033000 | Parallel Processing Array of Arithmetic Unit having a Barrier Instruction - A parallel processing array processor has a plurality of arithmetic units and a unit that manages barrier instructions whereby processing of program sequences may be coordinated. The array processor further comprises a hierarchy of assigned units whereby multiple program sequences may be processed in parallel. | 01-29-2015 |
20150074352 | Multiprocessor Having Segmented Cache Memory - A sequential data processor having a plurality of data processors, a plurality of memory segments, and a plurality of bus segments selectively interconnecting the data processors and memory segments to form a data cache. | 03-12-2015 |
20150082003 | Multiprocessor Having Associated RAM Units - A multiprocessor has a plurality of arithmetic units, each having two input registers and one output register, and a plurality of RAM units each having RAM memory and a pointer associated with the RAM memory such as a program pointer, an address pointer, a stack pointer or a subroutine claim pointer. | 03-19-2015 |