Patent application number | Description | Published |
20090057769 | CMOS DEVICE HAVING GATE INSULATION LAYERS OF DIFFERENT TYPE AND THICKNESS AND A METHOD OF FORMING THE SAME - In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level. | 03-05-2009 |
20090170339 | REDUCING THE CREATION OF CHARGE TRAPS AT GATE DIELECTRICS IN MOS TRANSISTORS BY PERFORMING A HYDROGEN TREATMENT - By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors. | 07-02-2009 |
20090218639 | SEMICONDUCTOR DEVICE COMPRISING A METAL GATE STACK OF REDUCED HEIGHT AND METHOD OF FORMING THE SAME - By providing a CMP stop layer in a metal gate stack, the initial height thereof may be efficiently reduced after the definition of the deep drain and source areas, thereby providing enhanced process conditions for forming highly stressed dielectric materials. Consequently, the dielectric material may be positioned more closely to the channel region substantially without deteriorating gate conductivity. | 09-03-2009 |
20100025770 | GATE DIELECTRICS OF DIFFERENT THICKNESS IN PMOS AND NMOS TRANSISTORS - By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage instability, hot carrier injection and the like, may be reduced. Due to the enhanced reliability of the P-channel transistors, overall production yield for a specified quality category may be increased, due to the possibility of selecting narrower guard bands for the semiconductor device under consideration. | 02-04-2010 |
20100077839 | IN SITU MONITORING OF METAL CONTAMINATION DURING MICROSTRUCTURE PROCESSING - By providing a tool internal sensor device in a process tool in a semiconductor facility, metal contamination may be monitored in situ, thereby avoiding or at least significantly reducing the requirement for sophisticated sample preparation techniques, such as vapor phase decomposition tests in combination with subsequent analysis procedures. Thus, a full time inspection of process tools may be accomplished. | 04-01-2010 |
20100221883 | ADJUSTING OF A NON-SILICON FRACTION IN A SEMICONDUCTOR ALLOY DURING TRANSISTOR FABRICATION BY AN INTERMEDIATE OXIDATION PROCESS - The concentration of a non-silicon species in a semiconductor alloy, such as a silicon/germanium alloy, may be increased after a selective epitaxial growth process by oxidizing a portion of the semiconductor alloy and removing the oxidized portion. During the oxidation, preferably the silicon species may react to form a silicon dioxide material while the germanium species may be driven into the remaining semiconductor alloy, thereby increasing the concentration thereof. Consequently, the threshold adjustment of sophisticated transistors may be accomplished with enhanced process uniformity on the basis of a given parameter setting for the epitaxial growth process while nevertheless providing a high degree of flexibility in adjusting the composition of the threshold adjusting material. In other cases, in addition to or alternatively to forming a threshold adjusting semiconductor alloy, a strain-inducing semiconductor alloy may also be provided with enhanced flexibility using the above-described process sequence. | 09-02-2010 |
20100244155 | MAINTAINING INTEGRITY OF A HIGH-K GATE STACK BY AN OFFSET SPACER USED TO DETERMINE AN OFFSET OF A STRAIN-INDUCING SEMICONDUCTOR ALLOY - In sophisticated transistor elements including a high-k gate metal stack, the integrity of the sensitive gate materials may be ensured by a spacer element that may be concurrently used as an offset spacer for defining a lateral offset of a strain-inducing semiconductor alloy. The cap material of the sophisticated gate stack may be removed without compromising integrity of the offset spacer by providing a sacrificial spacer element. Consequently, an efficient strain-inducing mechanism may be obtained in combination with the provision of a sophisticated gate stack with the required material integrity, while reducing overall process complexity compared to conventional strategies. | 09-30-2010 |
20100289089 | ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION - Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. | 11-18-2010 |
20100289090 | ENHANCING UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING STI STRUCTURES AFTER THE GROWTH PROCESS - When forming sophisticated gate electrode structures of transistor elements of different type, the threshold adjusting channel semiconductor alloy may be provided prior to forming isolation structures, thereby achieving superior uniformity of the threshold adjusting material. Consequently, threshold variability on a local and global scale of P-channel transistors may be significantly reduced. | 11-18-2010 |
20100327373 | UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING - Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned. | 12-30-2010 |
20110045665 | REDUCING THE CREATION OF CHARGE TRAPS AT GATE DIELECTRICS IN MOS TRANSISTORS BY PERFORMING A HYDROGEN TREATMENT - By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors. | 02-24-2011 |
20110049642 | WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS INCLUDING GATE DIELECTRICS OF DIFFERENT THICKNESS - In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided. | 03-03-2011 |
20110129970 | ENHANCING INTERFACE CHARACTERISTICS BETWEEN A CHANNEL SEMICONDUCTOR ALLOY AND A GATE DIELECTRIC BY AN OXIDATION PROCESS - In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material. | 06-02-2011 |
20120193727 | ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION - Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors. | 08-02-2012 |
20120282760 | ENHANCING INTERFACE CHARACTERISTICS BETWEEN A CHANNEL SEMICONDUCTOR ALLOY AND A GATE DIELECTRIC BY AN OXIDATION PROCESS - In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material. | 11-08-2012 |
20130126984 | Patterning of Sensitive Metal-Containing Layers With Superior Mask Material Adhesion by Providing a Modified Surface Layer - When patterning metal-containing material layers, such as titanium nitride, in critical manufacturing stages, for instance upon forming sophisticated high-k metal gate electrode structures or providing hard mask materials for patterning a metallization system, the surface adhesion of a resist material on the titanium nitride material may be improved by applying a controlled oxidation process. | 05-23-2013 |
20130267086 | PASSIVATING POINT DEFECTS IN HIGH-K GATE DIELECTRIC LAYERS DURING GATE STACK FORMATION - Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material deposition cycles to form a high-k dielectric layer above a semiconductor material layer, and introducing a passivating material into a gaseous precursor that is used for forming the high-k dielectric layer during at least one of the plurality of material deposition cycles. | 10-10-2013 |
20130277766 | MULTIPLE HIGH-K METAL GATE STACKS IN A FIELD EFFECT TRANSISTOR - When forming sophisticated high-k metal gate electrode structures, the threshold voltage characteristics are adjusted on the basis of a well-established high-k dielectric material with an appropriate layer thickness, for instance by incorporating an appropriate metal species. Thereafter, further high-k dielectric materials may be deposited, typically with a greater dielectric constant, so as to define the final CET and physical thickness. | 10-24-2013 |
20130288435 | CET AND GATE CURRENT LEAKAGE REDUCTION IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY HEAT TREATMENT AFTER DIFFUSION LAYER REMOVAL - When forming high-k metal gate electrode structures by providing the gate dielectric material in an early manufacturing stage, the heat treatment or anneal process may be applied after incorporating work function metal species and prior to capping the gate dielectric material with a metal-containing electrode material. In this manner, the CET for a given physical thickness for the gate dielectric layer may be significantly reduced. | 10-31-2013 |
20140246735 | METAL GATE STRUCTURE FOR SEMICONDUCTOR DEVICES - Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum. | 09-04-2014 |