Patent application number | Description | Published |
20080199834 | RICH AND CONCURRENT PC EXPERIENCES ON COMPUTING DEVICES - According to the present disclosure, users can have PC experiences on game consoles. For example, a game console can become a computing device dedicated to a server PC. PC capabilities, applications, programs, and even desktops can be remoted from the server PC to the game console, cached on the game console, and displayed on the game console display. Moreover, any devices native to either the server PC or the game console can be easily shared between the server PC and the console. Alternatively, a game console can be a concurrent computing device with a server PC, where only minimal content is stored on the gaming console, and minimal applications are remoted from the server PC to the game console. In either the dedicated or remoted case, various common features may be used, such as notifications sent from the server PC to the game console. | 08-21-2008 |
20080320334 | Transactional debugger for a transactional memory system - Various technologies and techniques are disclosed for providing a debugger for programs running under a transactional memory system. When running a particular program using the debugger, the system detects when a conflict occurs on at least one conflictpoint that was set in the particular program. A graphical user interface is provided that displays information related to the detected conflict. The graphical user interface can display transactional state and/or other details independently of a conflict. A conflictpoint can be assigned to one or more regions of source code in one or more transactions in the particular program. A conflictpoint can also be assigned to a particular variable in the particular program. When running the particular program in a debug mode, execution is stopped if a conflict occurs on any of the conflictpoints. | 12-25-2008 |
20090006406 | Memory transaction grouping - Various technologies and techniques are disclosed for providing a transaction grouping feature for use in programs operating under a transactional memory system. The transaction grouping feature is operable to allow transaction groups to be created that contain related transactions. The transaction groups are used to enhance performance and/or operation of the programs. For example, different locking and versioning mechanisms can be used with different transaction groups. When running transactions, a hardware transactional memory execution mechanism can be used for one transaction group while a software transactional memory execution mechanism used for another transaction group. | 01-01-2009 |
20090006750 | Leveraging transactional memory hardware to accelerate virtualization and emulation - Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter. | 01-01-2009 |
20090006751 | Leveraging transactional memory hardware to accelerate virtualization and emulation - Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. A central processing unit is provided with the transactional memory hardware. Code backpatching can be facilitated by providing transactional memory hardware that supports a facility to maintain private memory state and an atomic commit feature. Changes made to certain code are stored in the private state facility. Backpatching changes are enacted by attempting to commit all the changes to memory at once using the atomic commit feature. An efficient call return stack can be provided by using transactional memory hardware. A call return cache stored in the private state facility captures a host address to return to after execution of a guest function completes. A direct-lookup hardware-based hash table is used for the call return cache. | 01-01-2009 |
20090007057 | Object model for transactional memory - Various technologies and techniques are disclosed for providing an object model for transactional memory. The object model for transactional memory allows transactional semantics to be separated from program flow. Memory transaction objects created using the object model can live beyond the instantiating execution scope, which allows additional details about the memory transaction to be provided and controlled. Transactional memory can be supported even from languages that do not directly expose transactional memory constructs. This is made possible by defining the object model in one or more base class libraries and allowing the language that does not support transactional memory directly to use transactional memory through the object model. | 01-01-2009 |
20090007107 | Leveraging transactional memory hardware to accelerate virtualization emulation - Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. One or more central processing units are provided with transactional memory hardware that is operable to accelerate virtualization. The transactional memory hardware has a facility to maintain private state, a facility to render memory accesses from other central processing units visible to software, and support for atomic commit of the private state. The transactional memory hardware can be used, for example, to facilitate emulation of precise exception semantics. The private state is operable to enable an emulated state to remain inconsistent with an architectural state and only synchronized on certain boundaries. An optimized sequence of instructions is executed using chunk-accurate simulation to try and achieve a same end effect. | 01-01-2009 |
20090265156 | DYNAMICALLY VARYING SIMULATION PRECISION - Simulating a processor based system includes simulating first processor actions at a first precision level and detecting a first trigger. The simulation is dynamically changed to a second precision level that is different than the first precision level based on the first trigger. Second processor actions are simulated at the second precision level. | 10-22-2009 |
20100262801 | TYPE SYSTEM SUPPORT FOR MEMORY ISOLATION PERMISSIONS - An object reference is tagged with an isolation permission modifier. At least two permissions can be included, and in an example three permissions are included. In implementing the permissions, type modifiers for controlling access to type members through references pointing at an object are defined. One of the type modifiers is associated with each occurrence of a type name. Each of the of type modifiers defines a different access permission to restrict operations on the object to which the reference points. | 10-14-2010 |
20100332538 | HARDWARE ACCELERATED TRANSACTIONAL MEMORY SYSTEM WITH OPEN NESTED TRANSACTIONS - Hardware assisted transactional memory system with open nested transactions. Some embodiments described herein implement a system whereby hardware acceleration of transactions can be accomplished by implementing open nested transaction in hardware which respect software locks such that a top level transaction can be implemented in software, and thus not be limited by hardware constraints typical when using hardware transactional memory systems. | 12-30-2010 |
20100332721 | OPERATING SYSTEM VIRTUAL MEMORY MANAGEMENT FOR HARDWARE TRANSACTIONAL MEMORY - Operating system virtual memory management for hardware transactional memory. A method may be performed in a computing environment where an application running on a first hardware thread has been in a hardware transaction, with transactional memory hardware state in cache entries correlated by memory hardware when data is read from or written to data cache entries. The data cache entries are correlated to physical addresses in a first physical page mapped from a first virtual page in a virtual memory page table. The method includes an operating system deciding to unmap the first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction. | 12-30-2010 |
20100332807 | PERFORMING ESCAPE ACTIONS IN TRANSACTIONS - Performing non-transactional escape actions within a hardware based transactional memory system. A method includes at a hardware thread on a processor beginning a hardware based transaction for the thread. Without committing or aborting the transaction, the method further includes suspending the hardware based transaction and performing one or more operations for the thread, non-transactionally and not affected by: transaction monitoring and buffering for the transaction, an abort for the transaction, or a commit for the transaction. After performing one or more operations for the thread, non-transactionally, the method further includes resuming the transaction and performing additional operations transactionally. After performing the additional operations, the method further includes either committing or aborting the transaction. | 12-30-2010 |
20100332808 | MINIMIZING CODE DUPLICATION IN AN UNBOUNDED TRANSACTIONAL MEMORY SYSTEM - Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes. | 12-30-2010 |
20110145304 | EFFICIENT GARBAGE COLLECTION AND EXCEPTION HANDLING IN A HARDWARE ACCELERATED TRANSACTIONAL MEMORY SYSTEM - Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. Embodiments includes acts for writing to a card table outside of a transaction; handling garbage collection compaction occurring when a hardware transaction is active by using a common global variable and instructing one or more agents to write to the common global variable any time an operation is performed which may change an object's virtual address; acts for managing a thread-local allocation context; acts for handling exceptions while in a hardware assisted transaction. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction. | 06-16-2011 |
20110145498 | INSTRUMENTATION OF HARDWARE ASSISTED TRANSACTIONAL MEMORY SYSTEM - Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods further include at least one of generating metrics related to performance of the architecturally significant processor caches; implementing one or more debug exceptions related to performance of the architecturally significant processor caches; or implementing one or more transactional breakpoints related to performance of the architecturally significant processor caches as a result of utilizing the architecturally significant portions of the architecturally significant processor caches. | 06-16-2011 |
20110145530 | LEVERAGING MEMORY ISOLATION HARDWARE TECHNOLOGY TO EFFICIENTLY DETECT RACE CONDITIONS - One embodiment includes method acts for detecting race conditions. The method includes beginning a critical section, during which conflicting reads and writes should be detected to determine if a race condition has occurred. This is performed by executing at a thread one or more software instructions to place a software lock on data. As a result of executing one or more software instructions to place a software lock on data, several additional acts are performed. In particular, the thread places a software lock on the data locking the data for at least one of exclusive writes or reads by the thread. And, at a local cache memory local to the thread, the thread enters the thread's memory isolation mode enabling local hardware buffering of memory writes and monitoring of conflicting writes or reads to or from the cache memory to detect reads or writes by non-lock respecting agents. | 06-16-2011 |
20110145552 | Handling Operating System (OS) Transitions In An Unbounded Transactional Memory (UTM) Mode - In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed. | 06-16-2011 |
20110145637 | Performing Mode Switching In An Unbounded Transactional Memory (UTM) System - In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed. | 06-16-2011 |
20110145798 | DEBUGGING MECHANISMS IN A CACHE-BASED MEMORY ISOLATION SYSTEM - Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion. | 06-16-2011 |
20110161603 | MEMORY TRANSACTION GROUPING - Various technologies and techniques are described for providing a transaction grouping feature for use in programs operating under a transactional memory system. The transaction grouping feature is operable to allow transaction groups to be created that contain related transactions. The transaction groups are used to enhance performance and/or operation of the programs. Different locking and versioning mechanisms can be used with different transaction groups. When running transactions, a hardware transactional memory execution mechanism can be used for one transaction group while a software transactional memory execution mechanism used for another transaction group. | 06-30-2011 |
20120079215 | Performing Mode Switching In An Unbounded Transactional Memory (UTM) System - In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed. | 03-29-2012 |
20120084760 | TRANSACTIONAL DEBUGGER FOR A TRANSACTIONAL MEMORY SYSTEM - Various technologies and techniques are disclosed for providing a debugger for programs running under a transactional memory system. When running a particular program using the debugger, the system detects when a conflict occurs on at least one conflictpoint that was set in the particular program. A graphical user interface is provided that displays information related to the detected conflict. The graphical user interface can display transactional state and/or other details independently of a conflict. A conflictpoint can be assigned to one or more regions of source code in one or more transactions in the particular program. A conflictpoint can also be assigned to a particular variable in the particular program. When running the particular program in a debug mode, execution is stopped if a conflict occurs on any of the conflictpoints. | 04-05-2012 |
20120284485 | OPERATING SYSTEM VIRTUAL MEMORY MANAGEMENT FOR HARDWARE TRANSACTIONAL MEMORY - Operating system virtual memory management for hardware transactional memory. A system includes an operating system deciding to unmap a first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction. | 11-08-2012 |
20130238579 | EFFICIENT GARBAGE COLLECTION AND EXCEPTION HANDLING IN A HARDWARE ACCELERATED TRANSACTIONAL MEMORY SYSTEM - Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction. | 09-12-2013 |
20140195632 | IMMUTABLE SHARABLE ZERO-COPY DATA AND STREAMING - The environment and use of an immutable buffer. A computing entity acquires data or generates data and populates the data into the buffer, after which the buffer is classified as immutable. The classification protects the data populated within the immutable buffer from changing during the lifetime of the immutable buffer, and also protects the immutable buffer from having its physical address changed during the lifetime of the immutable buffer. As different computing entities consume data from the immutable buffer, they do so through views provided by a view providing entity. The immutable buffer architecture may also be used for streaming data in which each component of the streaming data uses an immutable buffer. Accordingly, different computing entities may view the immutable data differently without having to actually copy the data. | 07-10-2014 |
20140195741 | TYPE CASTING IN A MANAGED CODE SYSTEM - Type casting in a managed code system is described. The managed code system includes managed memory as well as shared memory located outside of the managed memory. The managed memory has multiple managed memory portions, each corresponding to a computing entity, such as a processes. The type system permits obtaining of data from shared memory using type casting to thereby assign the data a type that supports type casting. The type is a valid type casting type that satisfies certain requirements that allow the type to be assigned while maintaining type safety. | 07-10-2014 |
20140195766 | SHARED AND MANAGED MEMORY UNIFIED ACCESS - A managed memory in which multiple computing entities each have a corresponding entity-specific portion that is subject to garbage collection. An immutable buffer is located outside of managed memory. For a given computing entity, the corresponding managed memory portion contains entity-specific objects that can be accessed by a specific computing entity, but not by the other multiple computing entities. For one or more of the entity-specific managed memory portions, the portion also includes a reference to shared memory, such as an immutable buffer. The reference is structured to be ignored by the garbage collector, though the reference may appear just as a normal object in the managed memory portion. Thus, a unified memory access model is made possible in which the methods for a computing entity to access a regular object in managed memory is similar to how the computing entity accesses shared memory. | 07-10-2014 |
20140195862 | SOFTWARE SYSTEMS BY MINIMIZING ERROR RECOVERY LOGIC - Handing errors in program execution. The method includes identifying a set including a plurality of explicitly identified failure conditions. The method further includes determining that one or more of the explicitly identified failure conditions has occurred. As a result, the method further includes halting a predetermined first execution scope of computing, and notifying another scope of computing of the failure condition. An alternative embodiment may be practiced in a computing environment, and includes a method handing errors. The method includes identifying a set including a plurality of explicitly identified failure conditions. The method further includes determining that an error condition has occurred that is not in the set including a plurality of explicitly identified failure conditions. As a result, the method further includes halting a predetermined first execution scope of computing, and notifying another scope of computing of the failure condition. | 07-10-2014 |
20140196059 | CAPABILITY BASED DEVICE DRIVER FRAMEWORK - Enforcing limitations on hardware drivers. The method includes from a system kernel, assigning I/O resources to the system's root bus. From the root bus, the method further includes assigning a subset of the I/O resources to a device bus. Assigning a subset of the I/O resources to a device bus includes limiting the device bus to only be able to assign I/O resources that are assigned to it by the root bus. From the device bus, the method includes assigning I/O resources to a device through a device interface. | 07-10-2014 |
20140282448 | OPERATING SYSTEM SUPPORT FOR CONTRACTS - A front-end compiler compiles source code into intermediate code, that may later be compiled into binary code. The source code defines an execution scope and includes a contract. When a contract is encountered at runtime of an execution scope, further execution of that execution scope is conditioned on whether a predicate associated with the contract is true. The front-end compiler operates so as to preserve the contract so that the contract continues to be semantically structured such that the predicate may be removed from the intermediate language code. The contract may thus continue to be understood by semantic analysis of the contract. Thus, the predicate may be understood by static analysis tools that operate on the intermediate code. | 09-18-2014 |
20150039869 | Handling Operating System (Os) Transitions In An Unbounded Transactional Memory (Utm) Mode - In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed. | 02-05-2015 |