Patent application number | Description | Published |
20110031611 | EMBEDDED LAMINATED DEVICE - An electronic device includes at least one semiconductor chip, each semiconductor chip defining a first main face and a second main face opposite to the first main face. A first metal layer is coupled to the first main face of the at least one semiconductor chip and a second metal layer is coupled to the second main face of the at least one semiconductor chip. A third metal layer overlies the first metal layer and a fourth metal layer overlies the second metal layer. A first through-connection extends from the third metal layer to the fourth metal layer, the first through-connection being electrically connected with the first metal layer and electrically disconnected from the second metal layer. A second through-connection extends from the third metal layer to the fourth metal layer, the second through-connection being electrically connected with the second metal layer and electrically disconnected from the first metal layer. | 02-10-2011 |
20130011972 | METHOD OF PRODUCING LAMINATED DEVICE - A method of producing a laminate insert package includes providing a first metal layer, printing a first dielectric layer on the first metal layer, providing a second metal layer, printing a second dielectric layer on the second metal layer, and printing a dielectric spacer layer on the first dielectric layer. At least one semiconductor chip is attached to either the first or the second metal layer. A first layer assembly comprising the first metal layer, the first dielectric layer, the dielectric spacer layer and a second layer assembly comprising the second metal layer and the second dielectric layer are brought together. The first and second layer assemblies are laminated to form a laminate insert package, whereby the at least one semiconductor chip is embedded within the laminate insert package. | 01-10-2013 |
20130017651 | METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGEAANM Standing; MartinAACI VillachAACO ATAAGP Standing; Martin Villach ATAANM Ganitzer; PaulAACI VillachAACO ATAAGP Ganitzer; Paul Villach AT - A method for manufacturing a semiconductor package, the method comprising providing a substrate having opposite first and second surfaces and having one or more through openings formed therethrough from the first to the second surfaces at predefined positions; providing at least one first die having first and second opposite surfaces and having one or more first contact terminals on the first surface of the at least one first die; placing the at least one first die with the first surface thereof on the first surface of the substrate, with an adhesive applied therebetween outside the one or more through openings, such that the one or more through openings are aligned to the one or more first contact terminals, whereby a die assembly having correspondingly opposite first and second surfaces is formed; providing the first surface of the die assembly with a first plating layer of an electrically conductive plating material to electrically contact the one or more first contact terminals, wherein the plating material of the first plating layer extends in the through openings to electrically contact the one or more first contact terminals therethrough. | 01-17-2013 |
20130062706 | Electronic Module - An electronic module includes a first semiconductor chip and a passive component, wherein the first semiconductor chip is arranged on a surface of the passive component. | 03-14-2013 |
20130069243 | Chip Module and Method for Fabricating a Chip Module - The chip module includes a semiconductor chip having a first contact element on a first main face and a second contact element on a second main face. The semiconductor chip is arranged on a corner in such a way that the first main face of the semiconductor chip faces the carrier. One or more electrical connectors are connected to the carrier and include end faces located in a plane above a plane of the second main face of the semiconductor chip. | 03-21-2013 |
20130234283 | Semiconductor Packages and Methods of Forming The Same - In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate. | 09-12-2013 |
20140110820 | PASSIVE COMPONENT AS THERMAL CAPACITANCE AND HEAT SINK - Representative implementations of devices and techniques provide improved thermal performance of a chip die disposed within a layered printed circuit board (PCB). Passive components may be strategically located on one or more surfaces of the PCB. The passive components may be arranged to conduct heat generated by the chip die away from the chip die. | 04-24-2014 |
20140111951 | HIGH PERFORMANCE VERTICAL INTERCONNECTION - Representative implementations of devices and techniques provide improved electrical performance of components, such as chip dice, for example, disposed on different layers of a multi-layer printed circuit board (PCB). In an example, the components may be embedded within layers of the PCB. An insulating layer located between two component layers or sets of layers includes a conductive portion that may be strategically located to provide electrical connectivity between the components. The conductive portion may also be arranged to improve thermal conductivity between points of the PCB. | 04-24-2014 |
20140111955 | HIGH EFFICIENCY EMBEDDING TECHNOLOGY - Representative implementations of devices and techniques provide improved electrical access to components, such as chip dice, for example, disposed within layers of a multi-layer printed circuit board (PCB). One or more insulating layers may be located on either side of a spacer layer containing the components. The insulating layers may have apertures strategically located to provide electrical connectivity between the components and conductive layers of the PCB. | 04-24-2014 |
20140153206 | SYSTEMS AND METHODS FOR EMBEDDING DEVICES IN PRINTED CIRCUIT BOARD STRUCTURES - Embodiments relate to active devices embedded within printed circuit boards (PCBs). In embodiments, the active devices can comprise at least one die, such as a semiconductor die, and coupling elements for mechanically and electrically coupling the active device with one or more layers of the PCB in which the device is embedded. Embodiments thereby provide easy embedding of active devices in PCBs and inexpensive integration with existing PCB technologies and processes. | 06-05-2014 |
20140307391 | THREE DIMENSIONAL PACKAGING - Representative implementations of devices and techniques provide a printed circuit board (PCB) arranged to at least partly surround an electrical component having a plurality of non-coplanar outer surfaces. The PCB is arranged to fold at one or more predetermined boundaries. | 10-16-2014 |
20140311794 | POWER IN LEAD - Representative implementations of devices and techniques provide off-board power conversion. A power cable is arranged to distribute power from a power supply to a peripheral component. An active circuit is integrated into the cable, converting the power en route from the power supply to the peripheral component. | 10-23-2014 |
20150078042 | Power Supply and Method - A power supply includes a plurality of electronic components including one or more of a rectifier and a switching transistor, an input port configured to receive electrical energy from a power source and a circuit board comprising a cavity. At least one of the rectifier and the switching transistor is embedded in the cavity. The cavity is arranged proximal to the input port such that at least a portion of thermal energy generated by one or more of the rectifier and the switching transistor is dissipated from the power supply by way of the input port. | 03-19-2015 |
Patent application number | Description | Published |
20090008804 | Power semiconductor package - A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode. | 01-08-2009 |
20090174058 | CHIP SCALE PACKAGE - A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder. | 07-09-2009 |
20100102327 | Semiconductor device and passive component integration in a semiconductor package - According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate. | 04-29-2010 |
20120061725 | Power Semiconductor Package - A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can. | 03-15-2012 |
20130140701 | Solderable Contact and Passivation for Semiconductor Dies - A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites. | 06-06-2013 |
20130143399 | Method for Forming a Reliable Solderable Contact - A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites. | 06-06-2013 |
Patent application number | Description | Published |
20080224286 | Vertically mountable semiconductor device package - A semiconductor package that includes a die with electrodes on opposite surfaces thereof and respective conductive clip electrically and mechanically coupled to the electrode and configured for vertical mounting of the package. | 09-18-2008 |
20080230152 | PASTE FOR FORMING AN INTERCONNECT AND INTERCONNECT FORMED FROM THE PASTE - A paste for forming interconnects that includes a quantity of metallic binder particles, a quantity of metallic filler particles, and a quantity of flux. | 09-25-2008 |
20080230889 | SEMICONDUCTOR PACKAGE - A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive. | 09-25-2008 |
20090108821 | MULTI-PHASE VOLTAGE REGULATION MODULE - A voltage regulator module that includes components for a multi-phase converter, the converter including a plurality of power stage elements on one circuit board, a control element, driver elements, and elements for the output stages of the power stage elements on another circuit board. | 04-30-2009 |