Patent application number | Description | Published |
20100060321 | Clock control of state storage circuitry - State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry | 03-11-2010 |
20100083062 | High performance pulsed storage circuit - The application discloses state storage circuitry comprising: an operational data input for receiving input data, a diagnostic data input for receiving diagnostic data and a diagnostic select signal input; a storage element for storing a value indicative of data received from one of said operational data input and said diagnostic data input; an output for outputting said value stored in said storage element; a pulse generator for generating pulses in response to a clock signal, said pulse generator comprising a diagnostic output and a functional output and being responsive to receipt of a diagnostic enable signal at said diagnostic select signal input to output said generated pulses at said diagnostic output and being responsive to receipt of a diagnostic disable signal at said diagnostic select signal input to output said generated pulses at said functional output; an operational path switch for receiving said pulses from said functional output and being responsive to receipt of each of said pulses to provide a transmission path from said operational data input to said storage element and being responsive to receipt of no pulse to isolate said storage element from said operational data input; and a diagnostic path switch for receiving said pulses from said diagnostic output and being responsive to receipt of each of said pulses to provide a transmission path from said diagnostic data input to said storage element and being responsive to receipt of no pulse to isolate said storage element from said diagnostic data input. | 04-01-2010 |
20100088659 | Compensating for non-uniform boundary conditions in standard cells - A method of design of a standard cell and a standard cell is disclosed. The method design comprising the steps of: identifying a non-uniformity in a boundary condition of said standard cell that would affect a characteristic of a neighbouring standard cell; introducing a further non-uniformity into said cell to mitigate the effect of said identified non-uniform boundary condition on said characteristic of said neighbouring standard cell. | 04-08-2010 |
20100090260 | Integrated circuit layout pattern for cross-coupled circuits | 04-15-2010 |
20100095263 | Post-routing power supply modification for an integrated circuit - A technique for generating the layout of an integrated circuit | 04-15-2010 |
20100100861 | Modifying integrated circuit layout - A layout for an integrated circuit includes standard cells | 04-22-2010 |
20100115484 | Standard cell placement - A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit elements, providing a cell library defining a plurality of standard cells, each standard cell representing a potential component for forming the integrated circuit, providing compatibility information indicative of the compatibility of the boundaries of the standard cells, and generating a placement of standard cells in dependence on the functional data and the compatibility information to produce the layout such that no abutting cells have incompatible boundaries. | 05-06-2010 |