Patent application number | Description | Published |
20080224296 | Article and Panel Comprising Semiconductor Chips, Casting Mold and Methods of Producing the Same - A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer. | 09-18-2008 |
20080254575 | ENCAPSULATION METHOD AND APPARATUS - A method and apparatus for encapsulating items such as electronic devices. A mold material is dispensed onto the electronic device and the device is situated between first and second molds. One mold is moved towards the other so as to vary the size of a cavity defined by the first and second molds. A vacuum is applied to the cavity and the vacuum is varied in response to the size of the cavity. The vacuum can be varied in response to a predetermined vacuum profile. For example, in certain embodiments the vacuum is varied in response to the position of the first mold relative to the second mold, wherein the vacuum is increased as the cavity height is reduced. | 10-16-2008 |
20080265383 | Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged. | 10-30-2008 |
20080265421 | Structure for Electrostatic Discharge in Embedded Wafer Level Packages - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. | 10-30-2008 |
20090008793 | SEMICONDUCTOR DEVICE - A description is given of a device comprising a first semiconductor chip, a molding compound layer embedding the first semiconductor chip, a first electrically conductive layer applied to the molding compound layer, a through hole arranged in the molding compound layer, and a solder material filling the through hole. | 01-08-2009 |
20090014871 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment includes a semiconductor substrate and at least two insulating elements located above the semiconductor substrate or above a mold compound embedding the semiconductor substrate. The at least two insulating elements have a first face facing the semiconductor substrate or the mold compound and a second face facing away from the semiconductor substrate or the mold compound. A conductive element for each of the at least two insulating elements extends from the first face of the insulating element to the second face of the insulating element. | 01-15-2009 |
20090045511 | INTEGRATED CIRCUIT INCLUDING PARYLENE MATERIAL LAYER - An integrated circuit includes a substrate including a contact pad, a redistribution line coupled to the contact pad, and a dielectric material layer between the substrate and the redistribution line. The integrated circuit includes a solder ball coupled to the redistribution line and a parylene material layer sealing the dielectric material layer and the redistribution line. | 02-19-2009 |
20090079057 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a carrier defining a surface with a semiconductor chip including an integrated circuit attached to the carrier. An insulation layer is disposed over the carrier, extending above the surface of the carrier a first distance at a first location and a second distance at a second location. A transition area is defined between the first and second locations, wherein the transition area defines a non-right angle relative to the surface. | 03-26-2009 |
20090079089 | STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an opposing second surface. The second substrate includes an array of second connection elements on the first surface of the second substrate. The first connection elements is attached to the second connection elements; and is thinning at least one of the first substrate and the second substrate after the attachment of the first connection elements to the second connection elements. | 03-26-2009 |
20090091022 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR CHIP ASSEMBLY, AND METHOD FOR FABRICATING A DEVICE - A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element. | 04-09-2009 |
20090108440 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material. | 04-30-2009 |
20090155956 | SEMICONDUCTOR DEVICE - A semiconductor device and method. One embodiment provides an encapsulation plate defining a first main surface and a second main surface opposite to the first main surface. The encapsulation plate includes multiple semiconductor chips. An electrically conductive layer is applied to the first and second main surface of the encapsulation plate at the same time. | 06-18-2009 |
20090261468 | SEMICONDUCTOR MODULE - A semiconductor module. One embodiment provides at least two semiconductor chips placed on a carrier. The at least two semiconductor chips are then covered with a molding material to form a molded body. The molded body is thinned until the at least two semiconductor chips are exposed. Then, the carrier is removed from the at least two semiconductor chips. The at least two semiconductor chips are singulated. | 10-22-2009 |
20090294961 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip and a metal layer electrically coupled to the semiconductor chip. The semiconductor device includes an array of solder balls coupled to the metal layer and a front side protect material directly contacting the metal layer and laterally surrounding a portion of at least a plurality of solder balls. The front side protect material is configured to become fluid during solder reflow. | 12-03-2009 |
20100078777 | On-Chip Radio Frequency Shield with Interconnect Metallization - Structure and method for fabricating a system on chip with an on-chip RF shield including interconnect metallization is described. In one embodiment, the system on chip includes an RF circuitry disposed on a first portion of a top surface of a substrate, and a semiconductor circuitry disposed on a second portion of the top surface of the substrate. An interconnect RF barrier is disposed between the RF circuitry and the semiconductor circuitry, the interconnect RF barrier coupled to a ground potential node. | 04-01-2010 |
20100078778 | On-Chip RF Shields with Front Side Redistribution Lines - A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines. | 04-01-2010 |
20100193928 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a through-connection extending between a first main face of the semiconductor chip and a second main face of the semiconductor chip opposite the first main face, encapsulation material at least partially encapsulating the semiconductor chip, and a first metal layer disposed over the encapsulation material and connected with the through-connection. | 08-05-2010 |
20100207272 | SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE ELEMENT - A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion. | 08-19-2010 |
20100233831 | RECONFIGURED WAFER ALIGNMENT - A method of manufacturing semiconductor device comprises placing multiple chips onto a carrier. An encapsulation material is applied to the multiple chips and the carrier for forming an encapsulation workpiece. The encapsulation workpiece having a first main face facing the carrier and a second main face opposite to the first main face. Further, marking elements are applied to the encapsulation workpiece relative to the multiple chips, the marking elements being detectable on the first main face and on the second main face. | 09-16-2010 |
20100237506 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method. One embodiment provides a device including a semiconductor chip. A first conductor line is placed over the semiconductor chip. An external contact pad is placed over the first conductor line. At least a portion of the first conductor line lies within a projection of the external contact pad on the semiconductor chip. | 09-23-2010 |
20110024906 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR CHIP ASSEMBLY, AND METHOD FOR FABRICATING A DEVICE - A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element. | 02-03-2011 |
20110024915 | SEMICONDUCTOR DEVICE - A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole. | 02-03-2011 |
20110024918 | STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an opposing second surface. The second substrate includes an array of second connection elements on the first surface of the second substrate. The first connection elements is attached to the second connection elements; and is thinning at least one of the first substrate and the second substrate after the attachment of the first connection elements to the second connection elements. | 02-03-2011 |
20110068485 | COMPONENT AND METHOD FOR PRODUCING A COMPONENT - A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device. | 03-24-2011 |
20110285030 | METHOD FOR PRODUCING CHIP PACKAGES, AND CHIP PACKAGE PRODUCED IN THIS WAY - A method for producing chip packages is disclosed. In one embodiment, a plurality of chips is provided. The chips each have first pads. Second connection pads are applied on the wafer, wherein each second pad is electrically connected to a first pad. | 11-24-2011 |
20120104592 | SEMICONDUCTOR MODULE HAVING A SEMICONDUCTOR CHIP STACK AND METHOD - A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film. | 05-03-2012 |
20120202319 | MOLD APPARATUS AND METHOD - An apparatus and method for producing an article by molding is disclosed. In one embodiment, the method includes a mold with an upper part, a lower part and at least one mold cavity, and has a vacuum clamping ring with a least one closable vent, which is arranged between the upper part and the lower part. The mold cavity is at least partially filled with a mold material. The vent is closed, and the mold cavity is filled with a thermoplastic or thermoset material. | 08-09-2012 |
20120208320 | On-Chip RF Shields with Front Side Redistribution Lines - A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines. | 08-16-2012 |
20120235298 | ELECTRONIC DEVICE AND METHOD FOR PRODUCING A DEVICE - An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body. | 09-20-2012 |
20120256315 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR CHIP ASSEMBLY, AND METHOD FOR FABRICATING A DEVICE - A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element. | 10-11-2012 |
20120261841 | Article and Panel Comprising Semiconductor Chips, Casting Mold and Methods of Producing the Same - A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer. | 10-18-2012 |
20120286434 | BLANK INCLUDING A COMPOSITE PANEL WITH SEMICONDUCTOR CHIPS AND PLASTIC PACKAGE MOLDING COMPOUND AND METHOD AND MOLD FOR PRODUCING THE SAME - A blank and a semiconductor device include a composite panel with semiconductor chips embedded in a plastic package molding compound. The blank includes a composite panel with semiconductor chips arranged in rows and columns in a plastic package molding compound with active upper sides of the semiconductor chips forming a coplanar surface area with the upper side of the composite panel. The blank further includes an orientation indicator impressed into the plastic package molding compound when the semiconductor chips are embedded within the molding compound. | 11-15-2012 |
20130228904 | Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. | 09-05-2013 |
20140151700 | CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE - A chip package may include an interconnection layer having a first surface configured to face at least one chip, and a second surface opposite the first surface; at least one first pad and at least one second pad formed at at least one of the first surface and the second surface of the interconnection layer; at least one first conductive interconnect formed over the at least one first pad; and at least one second conductive interconnect formed over the at least one second pad, wherein a height of the at least one first conductive interconnect is less than a height of the at least one second conductive interconnect. | 06-05-2014 |
20140197530 | SEMICONDUCTOR DEVICE WITH CHIP HAVING LOW-K-LAYERS - A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer. | 07-17-2014 |
20140332937 | WORKPIECE WITH SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A WORKPIECE WITH SEMICONDUCTOR CHIPS - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. | 11-13-2014 |