Patent application number | Description | Published |
20080237871 | Method of Manufacturing a Semiconductor Device and Semiconductor Device Obtained With Such a Method - The invention relates to a method of manufacturing a semiconductor device ( | 10-02-2008 |
20080258186 | Source and Drain Formation in Silicon on Insulator Device - A silicon on insulator device has a silicon layer ( | 10-23-2008 |
20090302389 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH DIFFERENT METALLIC GATES - A method is described for forming gate structures with different metals on a single substrate. A thin semiconductor layer ( | 12-10-2009 |
20100028809 | DOUBLE PATTERNING FOR LITHOGRAPHY TO INCREASE FEATURE SPATIAL DENSITY - A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spartial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools. | 02-04-2010 |
20100044760 | SELF-ALIGNED IMPACT-IONIZATION FIELD EFFECT TRANSISTOR - An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by an intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region. | 02-25-2010 |
20120088344 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXY REGION - A method is described what includes providing a substrate having a first trench and a second trench. An epitaxy material (crystalline material) is formed in the first trench and in the second trench. The top surface of the epitaxy material in the first trench is noncollinear with a top surface of the epitaxy material in the second trench. An amorphous semiconductor layer is formed on the crystalline material. Subsequently, the amorphous layer is converted, in part or in whole, into the crystalline semiconductor material. In an embodiment, a planarization process after the conversion provides crystalline regions having a coplanar top surface. | 04-12-2012 |
20120319167 | Mask-less and Implant Free Formation of Complementary Tunnel Field Effect Transistors - A device includes a first source/drain region of a first conductivity type over a silicon substrate, wherein the first source/drain region is at a higher step of a two-step profile. The first source/drain region includes a germanium-containing region. A second source/drain region is of a second conductivity type opposite the first conductivity type, wherein the second source/drain region is at a lower step of the two-step profile. A gate dielectric includes a vertical portion in contact with a side edge the silicon substrate, and a horizontal portion in contact with a top surface of the silicon substrate at the lower step. The horizontal portion is connected to a lower end of the vertical portion. A gate electrode is directly over the horizontal portion, wherein a sidewall of the gate electrode is in contact with the vertical portion of the gate dielectric. | 12-20-2012 |
20120319211 | STRAINED CHANNEL FIELD EFFECT TRANSISTOR - The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features. | 12-20-2012 |
20130234205 | NICKELIDE SOURCE/DRAIN STRUCTURES FOR CMOS TRANSISTORS - A nickelide material with reduced resistivity is provided as source/drain contact surfaces in both NMOS and PMOS technology. The nickelide material layer may be a ternary material such as NiInAs, and may be formed from a binary material previously formed in the source/drain regions. The binary material may be the channel material or it may be an epitaxial layer formed over the channel material. The same ternary nickelide material may be used as the source/drain contact surface in both NMOS and PMOS transistors. Various binary or ternary channel materials may be used for the NMOS transistors and for the PMOS transistors. | 09-12-2013 |
20130256759 | Fin Structure for a FinFET Device - A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin. | 10-03-2013 |
20130256784 | MOSFETs with Channels on Nothing and Methods for Forming the Same - A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric. | 10-03-2013 |
20130299895 | III-V COMPOUND SEMICONDUCTOR DEVICE HAVING DOPANT LAYER AND METHOD OF MAKING THE SAME - A semiconductor device comprises a semiconductor substrate; a channel layer of at least one III-V semiconductor compound above the semiconductor substrate; a gate electrode above a first portion of the channel layer; a source region and a drain region above a second portion of the channel layer; and a dopant layer comprising at least one dopant contacting the second portion of the channel layer. | 11-14-2013 |
20140061801 | FIN FIELD EFFECT TRANSISTOR LAYOUT FOR STRESS OPTIMIZATION - The present disclosure describes a layout for stress optimization. The layout includes a substrate, at least two fin field effect transistors (FinFET) cells formed in the substrate, a FinFET fin designed to cross the two FinFET cells, a plurality of gates formed on the substrate, and an isolation unit formed between the first FinFET cell and the second FinFET cell. The two FinFET cells include a first FinFET cell and a second FinFET cell. The FinFET fin includes a positive charge FinFET (Fin PFET) fin and a negative charge FinFET (Fin NFET) fin. The isolation unit isolates the first FinFET cell from the second FinFET cell without breaking the FinFET fin. | 03-06-2014 |
20140138770 | Device with a Strained Fin - A device includes a wafer substrate having at least two isolation features, a buffer layer embedded between the two isolation features and a fin disposed over the buffer layer. The buffer layer includes a first lattice constant. The fin includes at least one pair of alternating layers having a compressive strained layer and a tensile strained layer such that the pair of alternating layer has a second lattice constant matching to the first lattice constant and remains strained at edge of the fin. The device further includes a gate disposed over the fin. The buffer layer, the compressive strained layer, and the tensile strained layer include element in Group III-V, or combination thereof. A thickness of the compressive strained layer or a thickness of the tensile strained layer is a function of the first lattice constant. | 05-22-2014 |
20140159165 | FACETED FINFET - Among other things, a semiconductor device comprising one or more faceted surfaces and techniques for forming the semiconductor device are provided. A semiconductor device, such as a finFET, comprises a fin formed on a semiconductor substrate. The fin comprises a source region, a channel, and a drain region. A gate is formed around the channel. A top fin portion of the fin is annealed, such as by a hydrogen annealing process, to create one or more faceted surfaces. For example the top fin portion comprises a first faceted surface formed adjacent to a second faceted surface at an angle greater than 90 degrees relative to the second faceted surface, which results in a reduced sharpness of a corner between the first faceted surface and the second faceted surface. In this way, an electrical field near the corner is substantially uniform to electrical fields induced elsewhere within the fin. | 06-12-2014 |
20140239347 | Structure and Method for Defect Passivation To Reduce Junction Leakage For FinFET Device - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species. | 08-28-2014 |
20140252478 | FinFET with Channel Backside Passivation Layer Device and Method - A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs. | 09-11-2014 |
20140264592 | Barrier Layer for FinFET Channels - Integrated circuit devices having FinFETs with channel regions low in crystal defects and current-blocking layers underneath the channels to improve electrostatic control. Optionally, an interface control layer formed of a high bandgap semiconductor is provided between the current-blocking layer and the channel. The disclosure also provides methods of forming integrated circuit devices having these structures. The methods include forming a FinFET fin including a channel by epitaxial growth, then oxidizing a portion of the fin to form a current-blocking layer. | 09-18-2014 |
20140264608 | DITCHES NEAR SEMICONDUCTOR FINS AND METHODS FOR FORMING THE SAME - A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor strip is between and contacting the isolation regions. A semiconductor fin overlaps, and is joined to, the semiconductor strip. A ditch extends from a top surface of the isolation regions into the isolation regions, wherein the ditch adjoins the semiconductor fin. | 09-18-2014 |
20140273383 | MOSFETs with Channels on Nothing and Methods for Forming the Same - A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer. | 09-18-2014 |