Patent application number | Description | Published |
20090182915 | Performing a Configuration Virtual Topology Change and Instruction Therefore - In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU. | 07-16-2009 |
20090198980 | FACILITATING PROCESSING IN A COMPUTING ENVIRONMENT USING AN EXTENDED DRAIN INSTRUCTION - An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. | 08-06-2009 |
20090210662 | MICROPROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR DIRECT PAGE PREFETCH IN MILLICODE CAPABLE COMPUTER SYSTEM - A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided. | 08-20-2009 |
20090210680 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MILLICODE STORE ACCESS CHECKING INSTRUCTIONS - A system, method and computer program product for a millicode store access checking instruction are provided. The system includes an operand access control register (OACR) including a test modifier indicator. The system also includes an instruction unit subsystem for fetching and decoding instructions. The instructions include a millicode instruction with an operand defining an address to check for a store access exception. The system further includes an execution unit to execute the millicode instruction. The execution unit performs a method. The method includes receiving the millicode instruction from the instruction unit subsystem, testing for the store access exception at the address as if the test modifier is set absent an update to the OACR, and outputting a result of the testing for the store access exception. | 08-20-2009 |
20090217009 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING STORAGE ELEMENTS - A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value. | 08-27-2009 |
20090217098 | MANAGING USE OF STORAGE BY MULTIPLE PAGEABLE GUESTS OF A COMPUTING ENVIRONMENT - Management of storage used by pageable guests of a computing environment is facilitated. An enhanced suppression-on-protection facility is provided that enables the determination of which level of protection (host or guest) caused a fault condition, in response to an attempted storage access. | 08-27-2009 |
20090217108 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROCESSING ERROR INFORMATION IN A SYSTEM - A system for processing errors in a processor comprising, a first register having a unique identifier operative to store a first error data, a processor operative to retrieve the first error data from the first register, associate the first error data with the unique identifier, and generate a first uniform error packet including the first error data and the unique identifier and a storage medium operative to store the first uniform error packet. | 08-27-2009 |
20090217110 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT INVOLVING ERROR THRESHOLDS - A system for processing errors in a processor comprising, an error counter, a pass counter, and a processing portion operative to determine whether a first error is active, increment an error counter responsive to determining that the first error is active, increment the pass counter responsive to determining that all errors have been checked, and clear the error counter responsive to determining that the pass counter is greater than or equal to a pass count threshold value. | 08-27-2009 |
20090300401 | PERFORMING A PERFORM TIMING FACILITY FUNCTION INSTRUCTION FOR SYCHRONIZING TOD CLOCKS - A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD clock with TOD clocks of other computer systems. The computer system comprises a memory; and, a processor in communications with the computer memory. The processor is capable of performing a PTFF instruction comprising: obtaining a function code specified in a first general register, the function code for identifying any one of a query function or a control function to be performed; obtaining, from a second general register, a memory address of a parameter block; responsive to the function code specifying a query function, storing timing information of the computer system in the parameter block according to the specified query function; responsive to the function code specifying a control function, using timing information obtained from the parameter block to perform the specified control function; and setting a condition code value indicating an outcome of the specified function. | 12-03-2009 |
20100095033 | PERFORMING A CONFIGURATION VIRTUAL TOPOLOGY CHANGE AND INSTRUCTION THEREFORE - In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU. | 04-15-2010 |
20100223448 | Computer Configuration Virtual Topology Discovery and Instruction Therefore - In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory. | 09-02-2010 |
20110246752 | Emulating Execution of An Instruction For Discovering Virtual Topology of a Logical Partitioned Computer System - In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory. | 10-06-2011 |
20110283280 | Executing an Instruction for Performing a Configuration Virtual Topology Change - In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of quest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU. | 11-17-2011 |
20110296114 | ATOMIC EXECUTION OVER ACCESSES TO MULTIPLE MEMORY LOCATIONS IN A MULTIPROCESSOR SYSTEM - A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data. | 12-01-2011 |
20110320638 | ENABLE/DISABLE ADAPTERS OF A COMPUTING ENVIRONMENT - An adapter is enabled for use. The enabling includes assigning one or more address spaces to the adapter, based on a request. For each address space assigned to the adapter, a corresponding device table entry is assigned. When the adapter is no longer needed, it is disabled and the assigned device table entries become available. | 12-29-2011 |
20110320652 | CONTROLLING ACCESS BY A CONFIGURATION TO AN ADAPTER FUNCTION - Access to an input/output adapter by a configuration is controlled. For each requested access to an adapter, checks are made to determine whether the configuration is authorized to access the adapter. If it is not authorized, then access is denied. If it is authorized, but access should be temporarily blocked, then instruction execution is altered to indicate such. If access is permitted, but should be blocked for another reason (other than temporarily), then access is denied. | 12-29-2011 |
20110320662 | IDENTIFICATION OF TYPES OF SOURCES OF ADAPTER INTERRUPTIONS - A source identification facility is provided that enables identification of the one or more types of adapters requesting an interrupt in order to facilitate processing of the interrupt. The adapter types are accessible to the operating system and are used to tailor processing by the operating system of the interrupt. | 12-29-2011 |
20110320663 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION TO A GUEST OPERATING SYSTEM - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used. | 12-29-2011 |
20110320664 | CONTROLLING A RATE AT WHICH ADAPTER INTERRUPTION REQUESTS ARE PROCESSED - The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on all central processing units in the configuration. The operating system processes the interruption, including examining and processing indicators of reported events until the operating system discontinues the suppression. This enables the operating system to control the number of pending interruptions and the number of processors processing those interruptions. | 12-29-2011 |
20110320755 | TRACKING DYNAMIC MEMORY REALLOCATION USING A SINGLE STORAGE ADDRESS CONFIGURATION TABLE - Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table. | 12-29-2011 |
20110320757 | STORE/STORE BLOCK INSTRUCTIONS FOR COMMUNICATING WITH ADAPTERS - Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter. | 12-29-2011 |
20110320764 | LOAD INSTRUCTION FOR COMMUNICATING WITH ADAPTERS - Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter. | 12-29-2011 |
20110320772 | CONTROLLING THE SELECTIVELY SETTING OF OPERATIONAL PARAMETERS FOR AN ADAPTER - An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block. | 12-29-2011 |
20110321061 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions. | 12-29-2011 |
20110321158 | GUEST ACCESS TO ADDRESS SPACES OF ADAPTER - An authorization mechanism allows a host executing a guest operating system to grant permission for the guest to directly access an adapter function's address spaces without host intervention. This access is via instructions implemented based on the architecture of the adapter function. The host also has the capability to intervene in the execution of the instruction, if desired. | 12-29-2011 |
20120036338 | FACILITATING PROCESSING IN A COMPUTING ENVIRONMENT USING AN EXTENDED DRAIN INSTRUCTION - An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. | 02-09-2012 |
20120047343 | USE OF TEST PROTECTION INSTRUCTION IN COMPUTING ENVIRONMENTS THAT SUPPORT PAGEABLE GUESTS - Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection. | 02-23-2012 |
20120173917 | PERFORMING A PERFORM TIMING FACILITY FUNCTION INSTRUCTION FOR SYNCHRONIZING TOD CLOCKS - A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes receiving, at a processing unit, a request to change a clock steering rate used to control a TOD-clock offset value for the processing unit, the TOD-clock offset defined as a function of a start time (s), a base offset (b), and a steering rate (r). The unit schedules a next episode start time with which to update the TOD-clock offset value. After updating TOD-clock offset value (d) at the scheduled time, TOD-clock offset value is added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator. | 07-05-2012 |
20120198114 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION TO A GUEST OPERATING SYSTEM - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used. | 08-02-2012 |
20120216022 | CONTROLLING THE SELECTIVELY SETTING OF OPERATIONAL PARAMETERS FOR AN ADAPTER - An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block. | 08-23-2012 |
20120221757 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions. | 08-30-2012 |
20120331261 | Point-in-Time Copying of Virtual Storage - A method includes making in a real storage, a copy of a first page content stored in a first page data structure by creating a second page content in a second data structure, the second page content pointing to actual data pointed to by the first page content, storing the second page content in the second data structure, marking the first page content in the first page data structure with a page protection bit, wherein the page protection bit prevents a modification of the virtual page, in response to an attempt to modify the virtual page, copying the virtual page in the event the first page content in the first page data structure is marked with the page protection bit, storing the copied virtual page in a second virtual storage, and altering the second page content in the second data structure to point to the stored virtual page. | 12-27-2012 |
20120331264 | Point-in-Time Copying of Virtual Storage and Point-in-Time Dumping - A method includes copying a first virtual storage by making, a point-in-time copy of a first page content stored in a first structure by creating a second page content in a second structure, the second page content pointing to actual data pointed to by the first page content, storing the second page content in the second data structure, marking the first page content in the first structure with a bit, copying the virtual page in the event the first page content in the first structure is marked with the bit, storing the copied virtual page in a second virtual storage, altering the second page content to point to the stored virtual page, and using the second virtual storage to perform the core dump process, wherein the second virtual storage is referenced via the second page content stored in the real storage. | 12-27-2012 |
20130014123 | DETERMINATION OF RUNNING STATUS OF LOGICAL PROCESSOR - An embodiment provides for operating an information processing system. An aspect of the invention includes allocating an execution interval to a first logical processor of a plurality of logical processors of the information processing system. The execution interval is allocated for use by the first logical processor in executing instructions on a physical processor of the information processing system. The first logical processor determines that a resource required for execution by the first logical processor is locked by another one of the other logical processors. An instruction is issued by the first logical processor to determine whether a lock-holding logical processor is currently running. The lock-holding logical processor waits to release the lock if it is currently running. A command is issued by the first logical processor to a super-privileged process for relinquishing the allocated execution interval by the first logical processor if the locking holding processor is not running. | 01-10-2013 |
20130024659 | Executing An Instruction for Performing a Configuration Virtual Topology Change - In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU. | 01-24-2013 |
20130138907 | USE OF TEST PROTECTION INSTRUCTION IN COMPUTING ENVIRONMENTS THAT SUPPORT PAGEABLE GUESTS - Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection. | 05-30-2013 |
20130185732 | PROVIDING BY ONE PROGRAM TO ANOTHER PROGRAM ACCESS TO A WARNING TRACK FACILITY - A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup. | 07-18-2013 |
20130185735 | WARNING TRACK INTERRUPTION FACILITY - A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup. | 07-18-2013 |
20130185736 | USE OF A WARNING TRACK INTERRUPTION FACILITY BY A PROGRAM - A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup. | 07-18-2013 |
20130185737 | PROVIDING BY ONE PROGRAM TO ANOTHER PROGRAM ACCESS TO A WARNING TRACK FACILITY - A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup. | 07-18-2013 |
20130185738 | USE OF A WARNING TRACK INTERRUPTION FACILITY BY A PROGRAM - A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup. | 07-18-2013 |
20130185739 | WARNING TRACK INTERRUPTION FACILITY - A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup. | 07-18-2013 |
20130246743 | DETERMINING THE STATUS OF RUN-TIME-INSTRUMENTATION CONTROLS - The invention relates to determining the status of run-time-instrumentation controls. The status is determined by executing a test run-time-instrumentation controls (TRIC) instruction. The TRIC instruction executed in either a supervisor state or a lesser-privileged state. The TRIC instruction determines whether the run-time-instrumentation controls have changed. The run-time-instrumentation controls are set to an initial value using a privileged load run-time-instrumentation controls (LRIC) instruction. The TRIC instruction is fetched and executed. If the TRIC instruction is enabled, then it is determined if the initial value set by the run-time-instrumentation controls has been changed. If the initial value set by the run-time-instrumentation controls has been changed, then a condition code is set to a first value. | 09-19-2013 |
20130246744 | MODIFYING RUN-TIME-INSTRUMENTATION CONTROLS FROM A LESSER-PRIVILEGED STATE - Embodiments of the invention relate to modifying run-time-instrumentation controls (MRIC) from a lesser-privileged state. The MRIC instruction is fetched. The MRIC instruction includes the address of a run-time-instrumentation control block (RICCB). The RICCB is fetched based on the address included in the MRIC instruction. The RICCB includes values for modifying a subset of the processor's run-time-instrumentation controls. The subset of run-time-instrumentation controls includes a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location. The RIB holds run-time-instrumentation information of the events recognized by the processor during program execution. The values of the RICCB are loaded into the run-time-instrumentation controls. Event information is provided to the RIB based on the values that were loaded in the run-time-instrumentation control. | 09-19-2013 |
20130246748 | DETERMINING THE STATUS OF RUN-TIME-INSTRUMENTATION CONTROLS - The invention relates to determining the status of run-time-instrumentation controls. The status is determined by executing a test run-time-instrumentation controls (TRIC) instruction. The TRIC instruction is executed in either a supervisor state or a lesser-privileged state. The TRIC instruction determines whether the run-time-instrumentation controls have changed. The run-time-instrumentation controls are set to an initial value using a privileged load run-time-instrumentation controls (LRIC) instruction. The TRIC instruction is fetched and executed. If the TRIC instruction is enabled, then it is determined if the initial value set by the run-time-instrumentation controls has been changed. If the initial value set by the run-time-instrumentation controls has been changed, then a condition code is set to a first value. | 09-19-2013 |
20130246755 | RUN-TIME INSTRUMENTATION REPORTING - Embodiments of the invention relate to run-time instrumentation reporting. An instruction stream is executed by a processor. Run-time instrumentation information of the executing instruction stream is captured by the processor. Run-time instrumentation records are created based on the captured run-time instrumentation information. A run-time instrumentation sample point of the executing instruction stream on the processor is detected. A reporting group is stored in a run-time instrumentation program buffer. The storing is based on the detecting and the storing includes: determining a current address of the run-time instrumentation program buffer, the determining based on instruction accessible run-time instrumentation controls; and storing the reporting group into the run-time instrumentation program buffer based on an origin address and the current address of the run-time instrumentation program buffer, the reporting group including the created run-time instrumentation records. | 09-19-2013 |
20130246769 | RUN-TIME INSTRUMENTATION MONITORING FOR PROCESSOR CHARACTERISTIC CHANGES - Embodiments of the invention relate to monitoring processor characteristic information of a processor using run-time-instrumentation. An aspect of the invention includes executing an instruction stream on the processor and detecting a run-time instrumentation sample point of the executing instruction stream on the processor. A reporting group is stored in a run-time instrumentation program buffer based on the run-time instrumentation sample point. The reporting group includes processor characteristic information associated with the processor. | 09-19-2013 |
20130246770 | CONTROLLING OPERATION OF A RUN-TIME INSTRUMENTATION FACILITY FROM A LESSER-PRIVILEGED STATE - Embodiments of the invention relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor. | 09-19-2013 |
20130246771 | RUN-TIME INSTRUMENTATION MONITORING OF PROCESSOR CHARACTERISTICS - Embodiments of the invention relate to monitoring processor characteristic information of a processor using run-time-instrumentation. An aspect of the invention includes executing an instruction stream on the processor and detecting a run-time instrumentation sample point of the executing instruction stream on the processor. A reporting group is stored in a run-time instrumentation program buffer based on the run-time instrumentation sample point. The reporting group includes processor characteristic information associated with the processor. | 09-19-2013 |
20130246776 | RUN-TIME INSTRUMENTATION REPORTING - Embodiments of the invention relate to run-time instrumentation reporting. An instruction stream is executed by a processor. Run-time instrumentation information of the executing instruction stream is captured by the processor. Run-time instrumentation records are created based on the captured run-time instrumentation information. A run-time instrumentation sample point of the executing instruction stream on the processor is detected. A reporting group is stored in a run-time instrumentation program buffer. The storing is based on the detecting and the storing includes: determining a current address of the run-time instrumentation program buffer, the determining based on instruction accessible run-time instrumentation controls; and storing the reporting group into the run-time instrumentation program buffer based on an origin address and the current address of the run-time instrumentation program buffer, the reporting group including the created run-time instrumentation records. | 09-19-2013 |
20130247013 | CONTROLLING OPERATION OF A RUN-TIME INSTRUMENTATION FACILITY FROM A LESSER-PRIVILEGED STATE - Embodiments of the invention relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor. | 09-19-2013 |
20130247014 | MODIFYING RUN-TIME-INSTRUMENTATION CONTROLS FROM A LESSER-PRIVILEGED STATE - Embodiments of the invention relate to modifying run-time-instrumentation controls (MRIC) from a lesser-privileged state. The MRIC instruction is fetched. The MRIC instruction includes the address of a run-time-instrumentation control block (RICCB). The RICCB is fetched based on the address included in the MRIC instruction. The RICCB includes values for modifying a subset of the processor's run-time-instrumentation controls. The subset of run-time-instrumentation controls includes a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location. The RIB holds run-time-instrumentation information of the events recognized by the processor during program execution. The values of the RICCB are loaded into the run-time-instrumentation controls. Event information is provided to the RIB based on the values that were loaded in the run-time-instrumentation control. | 09-19-2013 |
20130339673 | INTRA-INSTRUCTIONAL TRANSACTION ABORT HANDLING - Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction. | 12-19-2013 |
20140101400 | STORE PERIPHERAL COMPONENT INTERCONNECT (PCI) FUNCTION CONTROLS INSTRUCTION - An instruction is provided that includes an opcode field to identify a store instruction to store in a designated location current values of operational parameters of an adapter function of an adapter; a first field to identify a location, the contents of which include a function handle identifying a handle of the adapter function for which the store instruction is being performed, and an indication of an address space associated with the adapter function identified by the function handle to which the store instruction applies; and a second field to identify the designated location of where a result of the store instruction is to be stored. Execution of the instruction includes obtaining information from a function information block associated with the adapter function; and copying the information from the function information block into the designated location, based on completion of one or more validity checks with one or more predefined results. | 04-10-2014 |
20140149705 | USE OF TEST PROTECTION INSTRUCTION IN COMPUTING ENVIRONMENTS THAT SUPPORT PAGEABLE GUESTS - Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection. | 05-29-2014 |
20140281375 | RUN-TIME INSTRUMENTATION HANDLING IN A SUPERSCALAR PROCESSOR - A method and a computer program for a processor simultaneously handle multiple instructions at a time. The method includes labeling of an instruction ending a relevant sample interval from a plurality of such instructions. Further, the method utilizes a buffer to store N more number of entries than actually required, wherein, N refers to the number of RI instructions younger than the instruction ending a sample interval. Further, the method also includes the step of recording relevant instrumentation data corresponding to the sample interval and providing the instrumentation data in response to identification of the sample interval. | 09-18-2014 |
20140310475 | ATOMIC EXECUTION OVER ACCESSES TO MULTIPLE MEMORY LOCATIONS IN A MULTIPROCESSOR SYSTEM - A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data. | 10-16-2014 |
20140317325 | WARNING TRACK INTERRUPTION FACILITY - A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup. | 10-23-2014 |
20140337602 | Execution Of An Instruction For Performing a Configuration Virtual Topology Change - In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU. | 11-13-2014 |
20150026680 | Emulating Execution Of An Instruction For Discovering Virtual Topology Of A Logical Partitioned Computer System - In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory. | 01-22-2015 |
20150039868 | INTRA-INSTRUCTIONAL TRANSACTION ABORT HANDLING - Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction. | 02-05-2015 |