Patent application number | Description | Published |
20080318376 | Semiconductor Device Manufactured Using a Method to Improve Gate Doping While Maintaining Good Gate Profile - In one aspect, there is provided a method of manufacturing a semiconductor device. This method includes forming gate structures over a substrate, wherein the gate structures include gate electrodes located adjacent source/drain regions. A protective layer is formed over the gate structures and a CMP layer is formed over the protective layer. A portion of the CMP layer and the protective layer is removed to expose a portion of the gate electrodes with remaining portions of the CMP layer and the protective layer remaining over the source/drain regions. The exposed portion of the gate electrodes are doped with an n-type dopant or a p-type dopant, and the remaining portions of the CMP layer and the protective layer located over the source/drain regions are removed subsequent to the doping. | 12-25-2008 |
20090032877 | METHOD OF ENHANCING DRIVE CURRENT IN A TRANSISTOR - A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing. | 02-05-2009 |
20090053883 | METHOD OF SETTING A WORK FUNCTION OF A FULLY SILICIDED SEMICONDUCTOR DEVICE, AND RELATED DEVICE - A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 02-26-2009 |
20090170258 | METHODS FOR FULL GATE SILICIDATION OF METAL GATE STRUCTURES - One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed. | 07-02-2009 |
20100155860 | TWO STEP METHOD TO CREATE A GATE ELECTRODE USING A PHYSICAL VAPOR DEPOSITED LAYER AND A CHEMICAL VAPOR DEPOSITED LAYER - One embodiment of the present invention relates a semiconductor device formed by utilizing a two step deposition method for forming a gate electrode without causing damages to an underlying gate dielectric material. In one embodiment, a first layer of gate electrode material (first gate electrode layer) is formed onto the surface of a gate dielectric material using a deposition that does not damage the gate dielectric material (e.g., physical vapor deposition) thereby resulting in a damage free interface between the gate dielectric material and the gate electrode material. A second layer of gate electrode material (second gate electrode layer) is then formed onto the first layer of gate electrode material using a chemical deposition method that provides increased deposition control (e.g., good layer uniformity, impurity control, etc.). The first and second gate electrode layers are then selectively patterned to cumulatively form a semiconductor device's gate electrode. | 06-24-2010 |
20100187613 | Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device - A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 07-29-2010 |
20100237442 | SELECTIVELY SELF-ASSEMBLING OXYGEN DIFFUSION BARRIER - A shallow trench isolation structure is formed in a semiconductor substrate adjacent to an active semiconductor region. A selective self-assembling oxygen barrier layer is formed on the surface of the shallow trench isolation structure that includes a dielectric oxide material. The formation of the selective self-assembling oxygen barrier layer is selective in that it is not formed on the surface the active semiconductor region having a semiconductor surface. The selective self-assembling oxygen barrier layer is a self-assembled monomer layer of a chemical which is a derivative of alkylsilanes including at least one alkylene moiety. The silicon containing portion of the chemical forms polysiloxane, which is bonded to surface silanol groups via Si—O—Si bonds. The monolayer of the chemical is the selective self-assembling oxygen barrier layer that prevents diffusion of oxygen to a high dielectric constant material layer that is subsequently deposited as a gate dielectric. | 09-23-2010 |
20110111586 | Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device - A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 05-12-2011 |
20120196423 | METHOD OF FABRICATION BODIES FOR AN EMBEDDED POLYSILICON RESISTOR AND AN EMBEDDED eFUSE ISOLATED FROM A SUBSTRATE - A method includes providing a substrate having insulating layers thereon; forming a first trench in a first region of the substrate and a second trench in a second region of the substrate; thermally growing layers of oxide along the sides of the trenches; filling the first trench and the second trench with a polysilicon material, planarizing the polysilicon material, and creating a shallow trench isolation between the first region and the second region, wherein the step f) of creating the shallow trench isolation is performed only after the steps of d) filling and e) planarizing. | 08-02-2012 |
20120231590 | Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device - A method of setting a work function of a filly silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a suicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the suicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 09-13-2012 |