Patent application number | Description | Published |
20120124336 | SIGNAL PROCESSING SYSTEM AND INTEGRATED CIRCUIT COMPRISING A PREFETCH MODULE AND METHOD THEREFOR - A signal processing system comprising at least one master device at least one memory element and prefetch module arranged to perform prefetching from at least one memory element upon a memory access request to the at least one memory element from the at least one master device. Upon receiving a memory access request from the at least one master device, the prefetch module is arranged to configure the enabling of prefetching of at least one of instruction information and data information in relation to that memory access request based at least partly on an address to which the memory access request relates. | 05-17-2012 |
20120131241 | SIGNAL PROCESSING SYSTEM, INTEGRATED CIRCUIT COMPRISING BUFFER CONTROL LOGIC AND METHOD THEREFOR - A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorise the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritise respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered. | 05-24-2012 |
20130007532 | DATA PROCESSING SYSTEM HAVING A SEQUENCE PROCESSING UNIT AND METHOD OF OPERATION - A system includes one or more processors; one or more trace debug circuits configured to monitor one or more of instruction, data, and watchpoint buses of the one or more processors, and record information determined from said monitoring; and a sequence processing unit configured to provide a control signal to a trace debug circuit of the one or more trace debug circuits, wherein in response to the control signal, the trace debug circuit controls one or more of said monitoring and recording, and a system on a chip comprises the one or more processors, the one or more trace debug circuits, and the sequence processing unit. | 01-03-2013 |
20130007533 | DATA PROCESSING SYSTEM HAVING A SEQUENCE PROCESSING UNIT AND METHOD OF OPERATION - A system includes a processor configured to execute a first interrupt; an interrupt controller, coupled to the processor, and configured to store one or more pending interrupts; and a sequence processing unit, coupled to the processor and the interrupt controller, and configured to receive an identifier of the first interrupt, receive an identifier corresponding to each of the one or more pending interrupts, and provide trigger information to a state condition logic in response to one or more of the identifiers of the one or more pending interrupts and the identifier of the first interrupt, wherein the trigger information is used to determine a trace or debug action responsive to the trigger information. | 01-03-2013 |
20130097462 | EMBEDDED LOGIC ANALYZER - A logic analyzer embedded in a data processor includes a state processing unit for providing state machines for storing state conditions of functional blocks of the data processor and triggering sequences of states with corresponding actions based on True/False evaluation of state conditions. The configurations of the state machines that can be selected by the user include different combinations of a first clock frequency CLK | 04-18-2013 |
20130227256 | METHOD FOR SETTING BREAKPOINTS, AND AN INTEGRATED CIRCUIT AND DEBUG TOOL THEREFOR - A method for setting one or more breakpoints within executable program code of an embedded device is described. The method comprises copying at least one area of non-volatile memory (NVM) of the embedded device, comprising at least one instruction at which a breakpoint is to be set, into at least one area of overlay memory replacing within the overlay memory the at least one instruction at which a breakpoint is to be set with a breakpoint operation code, and enabling a mapping of the at least one area of NVM, comprising the at least one instruction at which a breakpoint is to be set, to the at least one area of overlay memory during execution of the program code within the embedded device. | 08-29-2013 |
20130232330 | METHOD FOR ENABLING CALIBRATION DURING START-UP OF A MICRO CONTROLLER UNIT AND INTEGRATED CIRCUIT THEREFOR - A method for enabling calibration during start-up of a micro controller unit device is provided. The method comprises, within the MCU device, reading overlay initialisation data from at least one memory element within an external support device operably coupled to the MCU device, and configuring memory mapping functionality of the MCU device to overlay data stored within at least a part of device memory of the MCU device with calibration data stored within the at least one memory element of the external support device in accordance with the overlay initialisation data. | 09-05-2013 |
20130246695 | INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM AND METHOD FOR PREFETCHING LINES OF DATA THEREFOR - An integrated circuit device comprising at least one prefetching module for prefetching lines of data from at least one memory element. The prefetching module is configured to determine a position of a requested block of data within a respective line of data of the at least one memory element, determine a number of subsequent lines of data to prefetch, based at least partly on the determined position of the requested block of data within the respective line of data of the at least one memory element, and cause the prefetching of n successive lines of data from the at least one memory element. | 09-19-2013 |
20140068345 | METHOD AND APPARATUS FOR FILTERING TRACE INFORMATION - In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria. | 03-06-2014 |