Patent application number | Description | Published |
20080244474 | Cell library management for power optimization - A method of managing a cell library regarding power optimization is disclosed. The method generally includes the steps of (A) reading a plurality of first modules within a first region of a circuit design stored in a design file, (B) calculating a first merit value indicating a relative sensitivity of the first region to a power consumption, the first merit value having a range from a static power dominated value to a dynamic power dominated value and (C) creating a constraint file configured to limit a design tool to a first subset of a plurality of replacement modules based on the first merit value such that the design tool automatically optimizes the power consumption of the first region by replacing at least one of the first modules with at least one of the replacement modules within the first subset, the replacement modules residing in a library file. | 10-02-2008 |
20090144682 | DUAL PATH STATIC TIMING ANALYSIS - A method to analyze timing in a circuit, generally including (A) simulating reception of an input signal and a clock signal at a first flip-flop, wherein (i) the input signal has a latest transition, (ii) the input signal arrives through a first path and (iii) the clock signal has an active edge, (B) calculating a value of a time difference between the latest transition and the active edge, (C) calculating a delay between the active edge and the latest transition appearing in an output signal, wherein (i) the delay is based on a model responding to the value, (ii) the model characterizes a clock-to-output delay as a function of the time difference and (iii) the characterization covering a range of values, (D) calculating an arrival time of the latest transition at a second flip-flop through a second signal path and (E) storing the arrival time in a recording medium. | 06-04-2009 |
20090164956 | REDISTRIBUTION OF CURRENT DEMAND AND REDUCTION OF POWER AND DCAP - A method to redistribute current demand is presented. The method includes a first step of determining timing arc data for one or more timing arcs of a circuit design. The method includes a second step of checking the timing arc data for delay shift target cells. The method includes a further step of swapping a delay shift target cell with a delay shift cell. | 06-25-2009 |
20090285047 | ROW DECODE DRIVER GRADIENT DESIGN IN A MEMORY DEVICE - A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The circuit variations are operable to reduce the leakage power of the driver by degrading performance thereof while maintaining required worst case timing. The worst case timing being defined by the timing and performance requirements for the most distant of the row decode driver circuits relative to the source of the applied row address signals. | 11-19-2009 |
20090288053 | METHODS OF CELL ASSOCIATION FOR AUTOMATED DISTANCE MANAGEMENT IN INTEGRATED CIRCUIT DESIGN - Associated methods and a computer program product are disclosed for modifying a design of an integrated circuit. Properties are assigned to cells in an integrated circuit design. The properties include a location constraint property and a timing constraint property. When a cell is moved and one or more properties are not in compliance, other cells are moved to restore the non-compliant properties to compliance. | 11-19-2009 |
20100007371 | TESTABLE TRISTATE BUS KEEPER - A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the opposite value to the tristate, applying the given value to the keeper element, capturing the first value, evaluating the second value using the first value, comparing the second value to the given value, and producing a failure code for the tristate when the second value is not equal to the given value. A passing code for the tristate is produced when a failure code has not been produced. | 01-14-2010 |
20100150271 | MODULATED CLOCK, AN IC INCLUDING THE MODULATED CLOCK AND A METHOD OF PROVIDING A MODULATED CLOCK SIGNAL FOR POWER CONTROL - A modulated clock, a method of providing a modulated clock signal, an integrated circuit including a modulated clock and a library of cells including a modulated clock. In one embodiment, the modulated clock includes (1) a clock controller configured to generate a digital control stream and (2) clock logic circuitry having a first input configured to receive a clock signal and a second input configured to receive the digital control stream. The clock logic circuitry is configured to provide a modulated clock signal in response to the clock signal and the digital control stream, wherein the modulated clock signal has an effective frequency that differs from the first frequency. | 06-17-2010 |
20100156494 | LATCH AND DFF DESIGN WITH IMPROVED SOFT ERROR RATE AND A METHOD OF OPERATING A DFF - A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and (3) tristate circuitry coupled to the passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, the Boolean logic gates configured to control operation of the single transistor pair based on the data input and a pulse clock signal to drive the feedbacks path. | 06-24-2010 |
20100157649 | TRANSISTOR BIT CELL ROM ARCHITECTURE - An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge transistor. The sense amplifier for determining the voltages on ROM bit lines may be a digital inverter, address decoding may be simplified since there are no timing requirements with respect to transistor pre-charge, and chips containing a plurality of ROM bit cell may be readily programmed. In one embodiment of the invention, each bit cell includes one PMOS transistor having its source in electrical connection with a voltage source, its drain connected or unconnected to a bit line, and its gate connected to an inverted version of the word line signal; and one NMOS transistor having its source connected to a lower voltage source, its drain connected or disconnected to the bit line, and its gate connected to the word line. The bit cell is programmed during the ROM generation by connecting the drain of either the PMOS (logic level 1) or the NMOS (logic level 0) to the bit line. | 06-24-2010 |
20100162058 | SEQUENTIAL ELEMENT LOW POWER SCAN IMPLEMENTATION - Disclosed herein is a sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes: (1) an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and (2) a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply. | 06-24-2010 |
20100169850 | ANALYZER AND METHODS FOR ARCHITECTURALLY INDEPENDENT NOISE SENSITIVITY ANALYSIS OF INTEGRATED CIRCUITS HAVING A MEMORY STORAGE DEVICE - Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes: (1) a circuit reservoir configured to receive and store a model of a circuit having at least one memory storage device to be analyzed, (2) a circuit parser configured to identify nodes of the model and (3) a circuit evaluator configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes. | 07-01-2010 |
20110128035 | CLOSED-LOOP SOFT ERROR RATE SENSITIVITY CONTROL - Disclosed is a closed-loop feedback system for controlling the soft error rate (SER) due to radiation strikes on electronic circuitry. A variable sensitivity soft error rate detector provides and output corresponding to the soft error rate. This output is supplied to a voltage control. The output of the voltage control is fed back to the sensitivity control of the sensor—thus forming a feedback loop. The output of the voltage control may be the power supply of the soft error rate sensor. The output of the soft error rate sensor may also be used to enable and disable fault tolerant schemes or alert a user. | 06-02-2011 |
20110304052 | POWER GRID OPTIMIZATION - A global power distribution network in an integrated circuit comprising a first layer of conductive material and a second layer of conductive material. The first layer of conductive material may be (i) coupled to one or more power supplies and (ii) configured to form a plurality of first rails of a mesh. The first rails may (a) supply power to one or more components of a core logic of the integrated circuit, (b) be aligned with a first axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh has a uniform voltage gradient from a perimeter of the integrated circuit to a center of the integrated circuit along the first axis. The second layer of conductive material may be (i) coupled to the one or more power supplies and (ii) configured to form a plurality of second rails of the mesh. The second rails may (a) supply power to one or more components of the core logic, (b) be aligned with a second axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh comprises a uniform voltage gradient from the perimeter of the integrated circuit to the center of the integrated circuit along the second axis. | 12-15-2011 |
20120008450 | FLEXIBLE MEMORY ARCHITECTURE FOR STATIC POWER REDUCTION AND METHOD OF IMPLEMENTING THE SAME IN AN INTEGRATED CIRCUIT - A memory for an integrated circuit, a method of designing a memory and an integrated circuit manufactured by the method. In one embodiment, the memory includes: (1) one of: (1a) at least one data input register block and at least one bit enable input register block and (1b) at least one data and bit enable merging block and at least one merged data register block, (2) one of: (2a) at least one address input register block and at least one binary to one-hot address decode block and (2b) at least one binary to one-hot address decode block and at least one one-hot address register block and (3) a memory array, at least one of the blocks having a timing selected to match at least some timing margins outside of the memory. | 01-12-2012 |
20120023473 | GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION - A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint. | 01-26-2012 |
20120119785 | INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR - One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides. | 05-17-2012 |
20120194217 | INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR - One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides. | 08-02-2012 |
20130249591 | SYSTEM AND METHOD FOR DECREASING SIGNAL INTEGRITY NOISE BY USING VARYING DRIVE STRENGTHS BASED ON LIKELIHOOD OF SIGNALS BECOMING VICTIMS - A method of designing an integrated circuit, integrated circuits using different drive strengths and a signal integrity monitor are provide herein. In one embodiment, the signal integrity monitor includes: (1) a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths and (2) a victim signal identifier configured to dynamically determine a potential victim signal path of the plurality of signal paths. | 09-26-2013 |
20140074449 | SCALABLE POWER MODEL CALIBRATION - A high-frequency supply voltage waveform is sampled from a functioning integrated circuit. This waveform is measured at (or coupled closely to) a power supply node on the integrated circuit. A low-frequency supply current waveform is sampled concurrently with the sampling the high-frequency supply voltage waveform. This waveform is measured at a power supply node external to the integrated circuit. A power supply network providing power to the integrated circuit is modeled with a circuit model. The power supply network is modeled using the high-frequency supply voltage waveform as an input to the circuit model. A simulation output is taken at a simulated power supply node corresponding to the power supply node external to said integrated circuit. Based on a comparison of the simulated low-frequency supply current waveform and the low-frequency supply current waveform, a value of at least one component of the circuit model is adjusted. | 03-13-2014 |
20140145775 | OVERSHOOT SUPPRESSION FOR INPUT/OUTPUT BUFFERS - Disclosed is a diode clamping circuit that is used in an I/O buffer to suppress noise. Diode-connected CMOS transistors or PN junction transistors are utilized, which are native to the CMOS process. Switching circuitry is also disclosed to isolate the diodes and prevent current drain in the circuit. Switching circuitry is also used to switch between two different power supply voltages. | 05-29-2014 |