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Mario M.

Mario M. Chiong Lay, Santiage CL

Patent application numberDescriptionPublished
20110224450SOLVENT-FREE PROCESS FOR OBTAINING PHOSPHOLIPIDS AND NEUTRAL ENRICHED KRILL OILS - Organic solvent-free processes for obtaining krill oil compositions are disclosed. The processes include a) cooking krill in a cooker vessel for a time and at a temperature sufficient to denature the protein content of the krill and cause a first solid krill fraction and a first liquid krill fraction to be formed while substantially avoiding emulsification of the first solid and first liquid hill fractions; b) removing the first solid and first liquid krill fractions from the cooker vessel at a temperature of at least about 90° C.; c) separating the first solid fraction and the first liquid fraction; and d) obtaining krill oil with neutral enriched from the first liquid fraction, and e) by pressing of first solid fraction to obtain press liquid or a second liquid krill fraction for obtaining hill oil with phospholipids enriched krill oil, the separating and the obtaining steps being carried out without the use of organic solvents. Krill oil compositions made by the process are also disclosed.09-15-2011

Mario M. Pelella, Mountain View, CA US

Patent application numberDescriptionPublished
20080247101ELECTRONIC DEVICE AND METHOD - An IO buffer is formed having a substrate resistor at a support layer of a semiconductor on insulator substrate. A diode junction is formed between the substrate resistor and portion of the semiconductor on insulator substrate underlying the substrate resistor. In the event of a high-voltage event, current will flow through the diode junction.10-09-2008
20080305613METHOD FOR FABRICATING AN SOI DEFINED SEMICONDUCTOR DEVICE - Methods are provided for fabricating a semiconductor on insulator (SOI) component on a semiconductor layer/insulator/substrate structure. The method includes forming one or more shallow trench isolation (STI) regions extending through the semiconductor layer to the insulator. First and second openings are etched through the STI and the insulator using the remaining SOI material in the semiconductor layer as an etch mask. N— and P-type ions are implanted into the substrate through the openings to form to form N-doped and P-doped regions therein, such as an anode and a cathode of a semiconductor diode structure. The N-doped and P-doped regions are closely spaced and precisely aligned to each other by the SOI material in the semiconductor layer. Electrical contacts are then made to the N-doped and P-doped regions.12-11-2008
20090073758SRAM CELLS WITH ASYMMETRIC FLOATING-BODY PASS-GATE TRANSISTORS - The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region. Furthermore, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant.03-19-2009
20090184372SOI SEMICONDUCTOR COMPONENTS AND METHODS FOR THEIR FABRICATION - SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.07-23-2009
20100084729INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES - A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.04-08-2010

Patent applications by Mario M. Pelella, Mountain View, CA US

Mario M. Pellela, Mountain View, CA US

Patent application numberDescriptionPublished
20100187586SOI DEVICE AND METHOD FOR ITS FABRICATION - A silicon on insulator (SOI) device is provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.07-29-2010

Mario M. Rathie, Belmont, MA US

Patent application numberDescriptionPublished
20090100602Self-ventilating self-cooling cushion apparatus - A self-ventilating and self-cooling cushion including a core formed of a monolithic block of a reticulated foam material having a porosity of between about five pores per linear inch and twenty-five pores per linear inch, and cover surrounding the core. The cover is formed from a material having a plurality of openings therethrough and each of the plurality of openings is dimensioned to allow air to flow freely by natural convection through the cover.04-23-2009