Patent application number | Description | Published |
20100327433 | High Density MIM Capacitor Embedded in a Substrate - An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor. | 12-30-2010 |
20110180926 | Microelectromechanical Systems Embedded in a Substrate - An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device. | 07-28-2011 |
20110210438 | Thermal Vias In An Integrated Circuit Package With An Embedded Die - In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts. | 09-01-2011 |
20110248405 | Selective Patterning for Low Cost through Vias - A block layer deposited on a substrate before deposition of metal lines and etching of a through via enables low cost fabrication of through vias in a substrate using isotropic etching processes. For example, wet etching of a glass substrate may be used to fabricate through glass vias without undercut from the wet etching shorting metal lines on the glass substrate. The block layer prevents contact between a conductive layer lining the through via with more than one metal line on the substrate. The manufacturing process allows stacking of devices on substrates such as glass substrates and connecting the devices with through vias. | 10-13-2011 |
20120075216 | INTEGRATED PASSIVES AND POWER AMPLIFIER - This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate. | 03-29-2012 |
20130032385 | METAL THIN SHIELD ON ELECTRICAL DEVICE - This disclosure provides systems and methods for forming a metal thin film shield over a thin film cap to protect electromechanical systems devices in a cavity beneath. In one aspect, a dual or multi layer thin film structure is used to seal a electromechanical device. For example, a metal thin film shield can be mated over an oxide thin film cap to encapsulate the electromechanical device and prevent degradation due to wafer thinning, dicing and package assembly induced stresses, thereby strengthening the survivability of the electromechanical device in the encapsulated cavity. During redistribution layer processing, a metal thin film shield, such as a copper layer, is formed over the wafer surface, patterned and metalized. | 02-07-2013 |
20130082799 | CROSS-SECTIONAL DILATION MODE RESONATORS AND RESONATOR-BASED LADDER FILTERS - Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations. | 04-04-2013 |
20130083044 | CROSS-SECTIONAL DILATION MODE RESONATORS - Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations. | 04-04-2013 |
20140028543 | COMPLEX PASSIVE DESIGN WITH SPECIAL VIA IMPLEMENTATION - This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces. | 01-30-2014 |
20140035892 | INCORPORATION OF PASSIVES AND FINE PITCH THROUGH VIA FOR PACKAGE ON PACKAGE - This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including package-on-packages (PoPs). The glass via bars can provide high density electrical interconnections in the PoPs. In some implementations, the glass via bars can include integrated passive components. Packaging methods employing glass via bars are also provided. | 02-06-2014 |
20140035935 | PASSIVES VIA BAR - This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including embedded wafer level packages. The glass via bars can provide high density electrical interconnections in a package. In some implementations, the glass via bars can include integrated passive components. Methods of fabricating glass via bars are provided. In some implementations, the methods can include patterning and etching photo-patternable glass substrates. Packaging methods employing glass via bars are also provided. | 02-06-2014 |
20140111064 | COMPOSITE DILATION MODE RESONATORS - This disclosure provides systems, methods and apparatus related to acoustic resonators that include composite transduction layers for enabling selective tuning of one or more acoustic or electromechanical properties. In one aspect, a resonator structure includes one or more first electrodes, one or more second electrodes, and a transduction layer arranged between the first and second electrodes. The transduction layer includes a plurality of constituent layers. In some implementations, the constituent layers include one or more first piezoelectric layers and one or more second piezoelectric layers. The transduction layer is configured to, responsive to signals provided to the first and second electrodes, provide at least a first mode of vibration of the transduction layer with a displacement component along the z axis and at least a second mode of vibration of the transduction layer with a displacement component along the plane of the x axis and they axis. | 04-24-2014 |
20140138792 | HYBRID TRANSFORMER STRUCTURE ON SEMICONDUCTOR DEVICES - Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer. | 05-22-2014 |
20140167273 | LOW PARASITIC PACKAGE SUBSTRATE HAVING EMBEDDED PASSIVE SUBSTRATE DISCRETE COMPONENTS AND METHOD FOR MAKING SAME - One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode. The DCC is embedded within an insulator layer, and a via coupling component electrically couples to the electrode. A first portion of the via coupling component extends beyond a first edge of the electrode, and a plurality of vias each having a first end couple to the first via coupling component. At least a first via of the plurality of vias couples to the first portion of the via coupling component that extends beyond the first edge of the electrode. Moreover, the plurality of vias each have a second end that electrically couple to a first outer metal layer, and at least a second portion of the via coupling component is positioned within a first inner metal layer. | 06-19-2014 |
20140197902 | DIPLEXER DESIGN USING THROUGH GLASS VIA TECHNOLOGY - A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate. | 07-17-2014 |
20140247269 | HIGH DENSITY, LOW LOSS 3-D THROUGH-GLASS INDUCTOR WITH MAGNETIC CORE - This disclosure provides systems, methods and apparatus for three-dimensional (3-D) through-glass via inductors. In one aspect, the through-glass via inductor includes a glass substrate with a first cavity, a second cavity, and at least two through-glass vias. The through-glass vias include metal bars that are connected by a metal trace. The metal bars and the metal trace define the inductor, and each cavity is at least partially filled with magnetic material. The magnetic material can include a plurality of particles having an average diameter of less than about 20 nm. The first cavity can be inside the inductor and the second cavity can be outside inductor. In some implementations, the first and the second cavity can be vias that extend only partially through the glass substrate. | 09-04-2014 |
20140266494 | INTEGRATION OF A REPLICA CIRCUIT AND A TRANSFORMER ABOVE A DIELECTRIC SUBSTRATE - A particular device includes a replica circuit disposed above a dielectric substrate. The replica circuit includes a thin film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The device further includes a transformer disposed above the dielectric substrate and coupled to the replica circuit. The transformer is configured facilitate an impedance match between the replica circuit and an antenna. | 09-18-2014 |
20140268615 | TWO-STAGE POWER DELIVERY ARCHITECTURE - A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator. | 09-18-2014 |
20140268616 | CAPACITOR WITH A DIELECTRIC BETWEEN A VIA AND A PLATE OF THE CAPACITOR - In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device. | 09-18-2014 |
20140327496 | TUNABLE DIPLEXERS IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DIC) AND RELATED COMPONENTS AND METHODS - Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used. | 11-06-2014 |
20140327508 | INDUCTOR TUNABLE BY A VARIABLE MAGNETIC FLUX DENSITY COMPONENT - An inductor tunable by a variable magnetic flux density component is disclosed. A particular device includes an inductor. The device further includes a variable magnetic flux density component (VMFDC) positioned to influence a magnetic field of the inductor when a current is applied to the inductor. | 11-06-2014 |
20140327510 | ELECTRONIC DEVICE HAVING ASYMMETRICAL THROUGH GLASS VIAS - An electronic device includes a structure. The structure includes a first set of through glass vias (TGVs) and a second set of TGVs. The first set of TGVs includes a first via and the second set of TGVs includes a second via. The first via has a different cross-sectional shape than the second via. | 11-06-2014 |
20140354372 | SYSTEMS FOR REDUCING MAGNETIC COUPLING IN INTEGRATED CIRCUITS (ICS), AND RELATED COMPONENTS AND METHODS - Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter. | 12-04-2014 |
20140354378 | DESIGN FOR HIGH PASS FILTERS AND LOW PASS FILTERS USING THROUGH GLASS VIA TECHNOLOGY - A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution. | 12-04-2014 |
20140361854 | COMPACT 3-D COPLANAR TRANSMISSION LINES - This disclosure provides systems, methods and apparatus for a compact 3-D coplanar transmission line (CTL). In one aspect, the CTL has a proximal end and a distal end separated, in a first plane, by a distance D, the first plane being parallel to a layout area of a substrate. The plane is defined by mutually orthogonal axes x and z The CTL provides a conductive path having pathlength L. D is substantially aligned along axis z, L is at least 1.5×D, and the CPW is configured such that at least one third of the pathlength L is disposed along one or more directions having a substantial component orthogonal to the first plane. Less than one third of the pathlength L is disposed in a direction having a substantial component parallel to axis x. | 12-11-2014 |
20140374914 | STRESS COMPENSATION PATTERNING - An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device. | 12-25-2014 |
20150014812 | THICK CONDUCTIVE STACK PLATING PROCESS WITH FINE CRITICAL DIMENSION FEATURE SIZE FOR COMPACT PASSIVE ON GLASS TECHNOLOGY - An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer. | 01-15-2015 |
20150035162 | INDUCTIVE DEVICE THAT INCLUDES CONDUCTIVE VIA AND METAL LAYER - An inductive device that includes a conductive via and a metal layer are disclosed. A particular method of forming an electronic device includes forming a metal layer that contacts a surface of a substrate. The substrate, including the surface, is formed from a substantially uniform dielectric material. The metal layer contacts a conductive via that extends at least partially within the substrate. The metal layer and the conductive via form at least a portion of an inductive device. | 02-05-2015 |
20150048480 | INTEGRATED PASSIVE DEVICE (IPD) ON SUBTRATE - Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer. | 02-19-2015 |
20150061813 | VARYING THICKNESS INDUCTOR - A particular device includes a substrate and a spiral inductor coupled to the substrate. The spiral inductor includes a first conductive spiral and a second conductive spiral overlaying the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate that is greater than the first thickness. A portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral. | 03-05-2015 |
20150070863 | LOW PACKAGE PARASITIC INDUCTANCE USING A THRU-SUBSTRATE INTERPOSER - An interposer for a chipset includes multilayer thin film capacitors incorporated therein to reduce parasitic inductance in the chipset. Power and ground terminals are laid out in a staggered pattern to cancel magnetic fields between conductive vias to reduce equivalent series inductance (ESL). | 03-12-2015 |