| Patent application number | Description | Published |
|---|
| 20090166721 | QUASI-VERTICAL GATED NPN-PNP ESD PROTECTION DEVICE - Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process. | 07-02-2009 |
| 20090256199 | LATERAL METAL OXIDE SEMICONDUCTOR DRAIN EXTENSION DESIGN - A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes. | 10-15-2009 |
| 20090256212 | LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC - An integrated circuit ( | 10-15-2009 |
| 20100006931 | VERTICAL DRAIN EXTENDED MOSFET TRANSISTOR WITH VERTICAL TRENCH FIELD PLATE - A vertical drain extended metal-oxide semiconductor field effect (MOSFET) transistor or a vertical double diffused metal-oxide semiconductor (VDMOS) transistor includes: a buried layer having a first conductivity type in a semiconductor backgate having a second conductivity type; an epitaxial (EPI) layer having the first conductivity type and formed above the buried layer; a deep well having the first conductivity type in the EPI layer extending down to the buried layer; at least one shallow well having the second conductivity type in the EPI layer; a shallow implant region having the first conductivity type and formed in the shallow well; a gate electrode having a lateral component extending over an edge of the shallow well and stopping at some spacing from an edge of the shallow implant and having a vertical trench field plate extending vertically into the EPI layer. | 01-14-2010 |
| 20100032728 | AREA EFFICIENT 3D INTEGRATION OF LOW NOISE JFET AND MOS IN LINEAR BIPOLAR CMOS PROCESS - Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability. | 02-11-2010 |
| 20100032729 | INTEGRATION OF HIGH VOLTAGE JFET IN LINEAR BIPOLAR CMOS PROCESS - A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed. | 02-11-2010 |
| 20100035421 | SEMICONDUCTOR WELL IMPLANTED THROUGH PARTIALLY BLOCKING MATERIAL PATTERN - A method for forming a partially blocking layer for an ion implantation process, which may be varied across the IC to form regions with different dopant concentrations, and regions with varying dopant concentrations in each contiguously implanted region, is disclosed. One or more temporary and/or permanent layers may form the partially blocking layer, including a combination of different materials such as polysilicon, silicon dioxide, silicon nitride, and photoresist. The partially blocking layer may be a uniform continuous sheet which transmits a uniform fraction of dopants, or a reticulated screen which transmits dopants through multiple open areas. Several partially blocking layers, each absorbing a different fraction of implanted dopants, may be formed on an IC to produce instances of a component with different performance parameters such as operation voltage, sheet resistance or gain. | 02-11-2010 |
| 20100148125 | METHOD OF FORMING SEMICONDUCTOR WELLS - A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer. | 06-17-2010 |
| 20100171149 | SYMMETRICAL BI-DIRECTIONAL SEMICONDUCTOR ESD PROTECTION DEVICE - A 2-terminal (i.e., anode, cathode) symmetrical bidirectional semiconductor electrostatic discharge (ESD) protection device is disclosed. The symmetrical bidirectional semiconductor ESD protection device design comprises a first and second shallow wells symmetrically spaced apart from a central floating well. Respective shallow wells comprise a first and second highly doped contact implant with opposite doping types (e.g., n-type, p-type). One or more field plates, connected to the central floating well, extend laterally outward from above the central well. The device can be used as an ESD protection device at a bidirectional I/O (e.g., in parallel with a symmetrical MOS to be protected). Upon an ESD event at an input node comprising the first and second shallow wells, a coupled npn-pnp bipolar component comprising the center well, the first and second shallow wells, and the first and second contact implants, is triggered, thereby shunting current from the first to the second shallow well. | 07-08-2010 |
| 20100200915 | LATERAL TRENCH MOSFET HAVING A FIELD PLATE - One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body region therebetween. A gate electrode region is disposed in a trench that extends beneath the surface of the semiconductor body at least partially between the source and drain. A gate dielectric separates the gate electrode region from the semiconductor body. In addition, a field plate region in the trench is coupled to the gate electrode region, and a field plate dielectric separates the field plate region from the semiconductor body. Other integrated circuits and methods are also disclosed. | 08-12-2010 |
| 20100252882 | MOS Transistor with Gate Trench Adjacent to Drain Extension Field Insulation - An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer. | 10-07-2010 |
| 20100264486 | FIELD PLATE TRENCH MOSFET TRANSISTOR WITH GRADED DIELECTRIC LINER THICKNESS - An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region. | 10-21-2010 |
| 20100314670 | STRAINED LDMOS AND DEMOS - An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <100> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress. | 12-16-2010 |
| 20110074493 | CONFIGURABLE NP CHANNEL LATERAL DRAIN EXTENDED MOS-BASED TRANSISTOR - An integrated circuit containing a configurable dual n/p-channel 3-D resurf high voltage MOS field effect transistor (MOSFET) is disclosed. An n-channel drain is coterminous with a p-channel source in an n-well, and a p-channel drain is coterminous with an n-channel source in a p-well. A lateral drift region including n-type drift lanes and p-type drift lanes extends between the n and p wells. A resurf layer abuts the lateral drift region. The n-channel MOS gate is separate from the p-channel MOS gate. The p-channel MOS gate may be operated as a field plate in the n-channel mode, and vice versa. An n-channel MOS transistor may be integrated into the n-channel MOS source to provide an n-channel cascode transistor configuration, and similarly for a p-channel cascode configuration, to debias parasitic bipolar transistors under the MOS gates. Circuits using the MOSFET with various loads are also disclosed. | 03-31-2011 |
| 20110076822 | LATERAL METAL OXIDE SEMICONDUCTOR DRAIN EXTENSION DESIGN - A semiconductor device | 03-31-2011 |
| 20110108914 | MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION - An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer. | 05-12-2011 |
| 20110111569 | MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION - An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer. | 05-12-2011 |
| 20110151634 | LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC - An integrated circuit ( | 06-23-2011 |
| 20110158439 | Silicon Microphone Transducer - A capacitive microphone transducer integrated into an integrated circuit includes a fixed plate and a membrane formed in or above an interconnect region of the integrated circuit. A process of forming an integrated circuit containing a capacitive microphone transducer includes etching access trenches through the fixed plate to a region defined for the back cavity, filling the access trenches with a sacrificial material, and removing a portion of the sacrificial material from a back side of the integrated circuit. | 06-30-2011 |
