Patent application number | Description | Published |
20110059116 | LASER-BASED VACCINE ADJUVANTS - The invention is directed to a vaccine for generating an enhanced immune response in a subject previously exposed to non-destructive laser radiation, as compared to an immune response in a subject previously non-exposed to non-destructive laser radiation. The invention is also directed to use of a composition comprising a vaccine for use in combination with non-destructive laser radiation for generating an enhanced immune response from a subject, as compared to an immune response without the use of laser radiation. The laser exposure acts as an adjuvant for the vaccine, increasing the efficacy and/or potency of the vaccine. | 03-10-2011 |
20130078265 | LASER-BASED VACCINE ADJUVANTS - The invention is directed to a vaccine for generating an enhanced immune response in a subject previously exposed to non-destructive laser radiation, as compared to an immune response in a subject previously non-exposed to non-destructive laser radiation. The invention is also directed to use of a composition comprising a vaccine for use in combination with non-destructive laser radiation for generating an enhanced immune response from a subject, as compared to an immune response without the use of laser radiation. The laser exposure acts as an adjuvant for the vaccine, increasing the efficacy and/or potency of the vaccine. | 03-28-2013 |
20140335110 | LASER-BASED VACCINE ADJUVANTS - The invention is directed to a vaccine for generating an enhanced immune response in a subject previously exposed to non-destructive laser radiation, as compared to an immune response in a subject previously non-exposed to non-destructive laser radiation. The invention is also directed to use of a composition comprising a vaccine for use in combination with non-destructive laser radiation for generating an enhanced immune response from a subject, as compared to an immune response without the use of laser radiation. The laser exposure acts as an adjuvant for the vaccine, increasing the efficacy and/or potency of the vaccine. | 11-13-2014 |
Patent application number | Description | Published |
20090300319 | APPARATUS AND METHOD FOR MEMORY STRUCTURE TO HANDLE TWO LOAD OPERATIONS - An apparatus and method to increase memory bandwidth is presented. In one embodiment, the apparatus comprises a load array having: a first array to store a plurality of load operation entries and a second array to store a second plurality of load operation entries. The apparatus further comprises: a store array having a plurality of store operation entries; a first address generation unit coupled to send a linear address of a first load operation to the first array and to send a linear address of a first store operation to the store array; and a second address generation unit coupled to send a linear address of a second load operation to the second array and to send a linear address of a second store operation to the store array. | 12-03-2009 |
20100146212 | Accessing a cache memory with reduced power consumption - In one embodiment, a cache memory includes a data array having N ways and M sets and at least one fill buffer coupled to the data array, where the data array is segmented into multiple array portions such that only one of the portions is to be accessed to seek data for a memory request if the memory request is predicted to hit in the data array. Other embodiments are described and claimed. | 06-10-2010 |
20100169382 | METAPHYSICAL ADDRESS SPACE FOR HOLDING LOSSY METADATA IN HARDWARE - A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache. | 07-01-2010 |
20100169579 | READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS - A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item. | 07-01-2010 |
20100169580 | MEMORY MODEL FOR HARDWARE ATTRIBUTES WITHIN A TRANSACTIONAL MEMORY SYSTEM - A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model. | 07-01-2010 |
20100169581 | EXTENDING CACHE COHERENCY PROTOCOLS TO SUPPORT LOCALLY BUFFERED DATA - A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible. | 07-01-2010 |
20110320723 | METHOD AND SYSTEM TO REDUCE THE POWER CONSUMPTION OF A MEMORY DEVICE - A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled. | 12-29-2011 |
20120117334 | READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS - A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item. | 05-10-2012 |
20120159079 | MEMORY MODEL FOR HARDWARE ATTRIBUTES WITHIN A TRANSACTIONAL MEMORY SYSTEM - A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model. | 06-21-2012 |
20130054899 | A 2-D GATHER INSTRUCTION AND A 2-D CACHE - A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor. The two-dimensional (2-D) cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a two-dimensional structure of the 2-D image. | 02-28-2013 |
20150178217 | 2-D Gather Instruction and a 2-D Cache - A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a 2-D image stored in a memory coupled to the processor. The 2-D cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a 2-D structure of the 2-D image. | 06-25-2015 |
Patent application number | Description | Published |
20130264464 | PHOTO-DETECTOR DEVICE AND A METHOD FOR BIASING A PHOTOMULTIPLIER TUBE - A photo-detector and method for operating same: the photo-detector comprises a photomultiplier tube comprising a plurality of electrodes, each having a photocathode, an anode, a first dynode, intermediate dynodes and a last dynode; and a biasing circuit that comprises a sequence of voltage follower elements, a voltage divider and a current source. The voltage divider is coupled across a high voltage power supply and different dynodes are coupled to different ones of the voltage follower elements, control inputs of which are coupled to different junctions of the voltage divider. The current source is coupled to the voltage divider, to the sequence of the voltage follower elements and to the cathode. The anode is coupled to a load element coupled to a positive pole of the high voltage power supply and arranged to receive an output signal of the anode and convert it to an output signal of the photo-detector. | 10-10-2013 |
20150145090 | SYSTEM AND METHOD FOR REDUCING DARK CURRENT DRIFT IN A PHOTODIODE BASED ELECTRON DETECTOR - A sensing element that may include (a) a PIN diode that may include an anode that is coupled to an anode contact; a cathode that is coupled to a cathode contact; a semiconductor portion that has a sensing region; and an insulator that is positioned between the cathode contact and the anode contact; and (b) a shielding element. The insulator, the cathode contact and the anode contact are positioned between the shielding element and the semiconductor portion. The shielding element is shaped and positioned to facilitate radiation to impinge onto the sensing region of the semiconductor portion while at least partially shielding the insulator from electrons that are emitted from the sensing region. | 05-28-2015 |
20150287841 | METHOD AND DEVICE FOR CONTROL OF AVALANCHE PHOTO-DIODE CHARACTERISTICS FOR HIGH SPEED AND HIGH GAIN APPLICATIONS - A device that may include A DC power supply coupled to a fixed current source; an avalanche photo-diode (APD); a DC voltage regulator that comprises a regulating transistor; wherein the DC voltage regulator is arranged to (a) maintain a regulated voltage at a fixed value, and (b) output the regulated voltage; and a temperature control module that is arranged to maintain a portion of the temperature control module at a fixed temperature; wherein the DC voltage regulator and the APD are electrically coupled in parallel to each other, so that a sum of currents that pass through the APD and the regulating transistor equals a fixed current supplied by the fixed current source; and wherein the portion of the temperature control module is thermally coupled to the DC voltage regulator and to the APD, and wherein APD and the regulating transistor are thermally coupled to each other. | 10-08-2015 |
20160076938 | METHOD AND DEVICE FOR CONTROL OF AVALANCHE PHOTO-DIODE CHARACTERISTICS FOR HIGH SPEED AND HIGH GAIN APPLICATIONS - A device that may include a DC power supply coupled to a fixed current source; an APD; a DC voltage regulator that comprises a regulating transistor, arranged to maintain a regulated voltage at a fixed value over different APD currents; a temperature control module that is arranged to maintain a portion of the temperature control module at a fixed temperature; and compensation circuit that comprises a compensation component that is thermally coupled to the APD. A voltage drop over the compensation component is smaller than a voltage drop over the APD. A sum of (a) a current that pass through the APD and (b) a current that passes through the compensation component is fixed. The portion of the temperature control module is thermally coupled to the compensation component and to the APD | 03-17-2016 |