Patent application number | Description | Published |
20090250844 | METHOD OF FABRICATING METAL- AND CERAMIC- MATRIX COMPOSITES AND FUNCTIONALIZED TEXTILES - A method of manufacturing an article comprises providing a first sheet, wetting the first sheet with a liquid precursor to provide a first wet sheet, and irradiating the first wet sheet in a pattern corresponding to a first cross section of the article such that the liquid precursor is at least partially converted to a solid in the first cross section. A second sheet is disposed adjacent to the first sheet. The method further comprises wetting the second sheet with the liquid precursor to provide a second wet sheet, and irradiating the second wet sheet in a pattern corresponding to a second cross section of the article such that the liquid precursor is at least partially converted to a solid in the second cross section. In particular the liquid precursor may be converted to a metal, ceramic, semiconductor, semimetal, or a combination of these materials. | 10-08-2009 |
20090256134 | Process for Fabricating Nanowire Arrays - A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced. | 10-15-2009 |
20090296189 | Designing the Host of Nano-Structured Optoelectronic Devices to Improve Performance - A nanostructured optoelectronic device is provided which comprises a nanostructured material and a host material intermingled with the nanostructured material. The host material may have a higher index of refraction than the nanostructured material. The host material's index of refraction may be chosen to maximize the effective active area of the device. In an alternative embodiment, the host material comprises scattering centers or absorption/luminescence centers which absorb light and reemit the light at a different energy or both. | 12-03-2009 |
20100092888 | Process for Structuring Silicon - A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H | 04-15-2010 |
20100122725 | Nanostructured Devices - A photovoltaic device is provided. It comprises at least two electrical contacts, p type dopants and n type dopants. It also comprises a bulk region and nanowires in an aligned array which contact the bulk region. All nanowires in the array have one predominant type of dopant, n or p, and at least a portion of the bulk region also comprises that predominant type of dopant. The portion of the bulk region comprising the predominant type of dopant typically contacts the nanowire array. The photovoltaic devices' p-n junction would then be found in the bulk region. The photovoltaic devices would commonly comprise silicon. | 05-20-2010 |
20100289060 | METHOD OF FABRICATING FREE-FORM, HIGH-ASPECT RATIO COMPONENTS FOR HIGH-CURRENT, HIGH-SPEED MICROELECTRONICS - Microelectronic structures and devices, and method of fabricating a three-dimensional microelectronic structure is provided, comprising passing a first precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures to enhance formation of a first portion of said three-dimensional microelectronic structure; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said first portion of a selected three-dimensional microelectronic structure is formed from said first precursor material; positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs; passing a second precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures whereby a second portion of said three-dimensional microelectronic structure formation is enhanced; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said second portion of a selected three-dimensional microelectronic structure is formed from said second precursor material; and, positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs. | 11-18-2010 |
20110024169 | SILICON NANOWIRE ARRAYS ON AN ORGANIC CONDUCTOR - In an aspect of the invention, a process to make a nanowire array is provided. In the process, silicon is deposited onto a conductive substrate comprising an organic material and optionally a conductive layer, thus forming a silicon-containing layer. Nanoparticles are deposited on top of the silicon-containing layer. Metal is deposited on top of the nanoparticles and silicon in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is contacted with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent. | 02-03-2011 |
20110232756 | DESIGNING THE HOST OF NANO-STRUCTURED OPTOELECTRONIC DEVICES TO IMPROVE PERFORMANCE - A nanostructured optoelectronic device is provided which comprises a nanostructured material and a host material intermingled with the nanostructured material. The host material may have a higher index of refraction than the nanostructured material. The host material's index of refraction may be chosen to maximize the effective active area of the device. In an alternative embodiment, the host material comprises scattering centers or absorption/luminescence centers which absorb light and reemit the light at a different energy or both. | 09-29-2011 |
20110278534 | OPTOELECTRONIC DEVICES UTILIZING MATERIALS HAVING ENHANCED ELECTRONIC TRANSITIONS - An optoelectronic device that includes a material having enhanced electronic transitions. The electronic transitions are enhanced by mixing electronic states at an interface. The interface may be formed by a nano-well, a nano-dot, or a nano-wire. | 11-17-2011 |
20120153250 | Nanowire Device with Alumina Passivation Layer and Methods of Making Same - In one aspect, the present disclosure relates to a device including a silicon substrate, wherein at least a portion of the substrate surface can be a silicon nanowire array; and a layer of alumina covering the silicon nanowire array. In some embodiments, the device can be a solar cell. In some embodiments, the device can be a p-n junction. In some embodiments, the p-n junction can be located below the bottom surface the nanowire array. | 06-21-2012 |
20120153251 | SELECTIVE EMITTER NANOWIRE ARRAY AND METHODS OF MAKING SAME - Another aspect of the present disclosure relates to a device including a substrate, having a top surface and a bottom surface; an array of nanowires having a base and a top surface, the base contacting the top surface of the substrate; a contacting structure including the same material as the substrate having a non-nanostructured surface of a dimension suitable for forming an electrical contact, located on the same side of the substrate as the array of silicon nanowires; wherein the contacting structure is doped with a greater impurity concentration than the nanowire array, thereby forming a selective emitter. | 06-21-2012 |
20120181502 | METHOD OF ELECTRICALLY CONTACTING NANOWIRE ARRAYS - In one aspect, the present disclosure relates to a device including a substrate, having a top surface and a bottom surface; an array of nanowires having a base and a top surface, the base contacting the top surface of the substrate; a contacting structure having a non-nanostructured surface, having a top surface and a bottom surface, located on the same side of the substrate as the array of silicon nanowires; and an electrical contact in contact with the top surface of the contacting structure. In some embodiments, the device includes an aluminum oxide passivation layer over the array of nanowires. In some embodiments, the layer of aluminum oxide is deposited via atomic layer deposition. | 07-19-2012 |
20120301785 | PROCESS FOR FABRICATING NANOWIRE ARRAYS - A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced. | 11-29-2012 |
20130099345 | ELECTRICAL CONTACTS TO NANOSTRUCTURED AREAS - A process is provided for contacting a nanostructured surface. In that process, a substrate is provided having a nanostructured material on a surface, the substrate being conductive and the nanostructured material being coated with an insulating material. A portion of the nanostructured material is at least partially removed. A conductor is deposited on the substrate in such a way that it is in electrical contact with the substrate through the area where the nanostructured material has been at least partially removed. | 04-25-2013 |
20130247966 | Nanostructured devices - A photovoltaic device is provided. It comprises at least two electrical contacts, p type dopants and n type dopants. It also comprises a bulk region and nanowires in an aligned array which contact the bulk region. All nanowires in the array have one predominant type of dopant, n or p, and at least a portion of the bulk region also comprises that predominant type of dopant. The portion of the bulk region comprising the predominant type of dopant typically contacts the nanowire array. The photovoltaic devices' p-n junction would then be found in the bulk region. The photovoltaic devices would commonly comprise silicon. | 09-26-2013 |
20140252564 | Process for Structuring Silicon - A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H | 09-11-2014 |
20140332068 | SCREEN PRINTING ELECTRICAL CONTACTS TO NANOWIRE AREAS - A process is provided for contacting a nanostructured surface. The process may include (a) providing a substrate having a nanostructured material on a surface, (b) passivating the surface on which the nanostructured material is located, (c) screen printing onto the nanostructured surface and (d) firing the screen printing ink at a high temperature. In some embodiments, the nanostructured material compromises silicon. In some embodiments, the nanostructured material includes silicon nanowires. In some embodiments, the nanowires are around 150 nm, 250 nm, or 400 nm in length. In some embodiments, the nanowires have a diameter range between about 30 nm and about 200 nm. In some embodiments, the nanowires are tapered such that the base is larger than the tip. In some embodiments, the nanowires are tapered at an angle of about 1 degree, about 3 degrees, or about 10 degrees. In some embodiments, a high temperature can be approximately 700C, 750C, 800C, or 850C. | 11-13-2014 |
20140335412 | PROCESS FOR FABRICATING NANOWIRE ARRAYS - A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced. | 11-13-2014 |
20140366934 | SELECTIVE EMITTER NANOWIRE ARRAY AND METHODS OF MAKING SAME - Another aspect of the present disclosure relates to a device including a substrate, having a top surface and a bottom surface; an array of nanowires having a base and a top surface, the base contacting the top surface of the substrate; a contacting structure including the same material as the substrate having a non-nanostructured surface of a dimension suitable for forming an electrical contact, located on the same side of the substrate as the array of silicon nanowires; wherein the contacting structure is doped with a greater impurity concentration than the nanowire array, thereby forming a selective emitter. | 12-18-2014 |
20150017802 | Double-etch nanowire process - In an aspect of this disclosure, a method is provided comprising the steps of: (a) providing a silicon-containing substrate, (b) depositing a first metal on the substrate, (c) etching the substrate produced by step (b) using a first etch, and (d) etching the substrate produced by step (c) using a second etch, wherein the second etch is more aggressive towards the deposited metal than the first etch, wherein the result of step (d) comprises silicon nanowires. The method may further comprise, for example, steps (b1) subjecting the first metal to a treatment which causes it to agglomerate and (b2) depositing a second metal. | 01-15-2015 |