Patent application number | Description | Published |
20100332923 | SYSTEM AND METHOD RESPONSIVE TO A RATE OF CHANGE OF A PERFORMANCE PARAMETER OF A MEMORY - Systems and methods are disclosed that are responsive to a rate of change of a performance parameter of a memory. In a particular embodiment, a rate of change of a performance parameter of a non-volatile memory is determined. The rate of change is compared to a threshold, and an action is performed in response to determining that the rate of change satisfies the threshold. | 12-30-2010 |
20100332943 | METHOD AND DEVICE FOR SELECTIVELY REFRESHING A REGION OF A NON-VOLATILE MEMORY OF A DATA STORAGE DEVICE - A method and device for selectively refreshing a region of a non-volatile memory of a data storage device is disclosed. In a particular embodiment, a method is disclosed that includes comparing a time stamp received from a host device to a first time stamp retrieved from a data storage device for a first region of a non-volatile memory, the first region including a least recently accessed region of a memory array within the data storage device. The method also includes selectively refreshing the first region based on a comparison of a difference between the time stamp received from the host device and the first time stamp as compared to a threshold, where the threshold is adjusted based on a first error count corresponding to a number of errors detected by an error correction code (ECC) engine with respect to data retrieved from the first region. | 12-30-2010 |
20100332949 | SYSTEM AND METHOD OF TRACKING ERROR DATA WITHIN A STORAGE DEVICE - Systems and methods of tracking error data are disclosed. A method includes receiving a first checksum associated with error locations of a first error correction code operation and receiving a second checksum associated with error locations of a second error correction code operation. The first checksum is compared to the second checksum and an action is initiated on a region of a memory array based on a result of the comparison. | 12-30-2010 |
20110185251 | SYSTEM AND METHOD TO CORRECT DATA ERRORS USING A STORED COUNT OF BIT VALUES - In a particular embodiment, at a controller coupled to a memory array, a method includes receiving an indication that a first group of data bits read from the memory array includes errors that are uncorrectable by an error correction coding (ECC) engine. A count of the first group of data bits having a particular bit value may be compared to a prior count of data bits having the particular bit value. In response to determining that the count exceeds the prior count, a bit of the first group of data bits that has the particular bit value and that corresponds to a same memory cell as a corrected data bit of a second group of data bits is identified. A value of the identified bit of the first group may be changed to generate an adjusted group of data bits. The adjusted group of data bits may be provided to the ECC engine. | 07-28-2011 |
20120084622 | SYSTEM AND METHOD OF DATA ENCODING - A method includes reading data from a data area of a word line and reading first ECC data from an ECC area of the word line. The method also includes, in response to determining that an error indicator exceeds a threshold, storing second ECC data in the ECC area. The second ECC data corresponds to a subsection of the data area. | 04-05-2012 |
20120102379 | SYSTEM AND METHOD OF INTERLEAVING DATA ACCORDING TO AN ADJUSTABLE PARAMETER - A method in a data storage device with a memory includes receiving bit values to be stored at a set of cells of the memory and interleaving the received bit values to form multiple interleaved groups of data bits according to an adjustable parameter. The method also includes writing the multiple interleaved groups of data bits to the set of cells. | 04-26-2012 |
20120204077 | DATA RECOVERY USING ADDITIONAL ERROR CORRECTION CODING DATA - A method in a data storage device receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and a second sub-block of data. The method also includes initiating an ECC operation to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data block, first additional ECC data that is external to the data block is retrieved and a second ECC operation is initiated to process the first sub-block of data using the first additional ECC data. | 08-09-2012 |
20130003480 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core. | 01-03-2013 |
20130007349 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core. | 01-03-2013 |
20130007350 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a first semiconductor device including a memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the memory core. The second semiconductor device includes a second serializer/deserializer communication interface coupled to a first serializer/deserializer communication interface of a memory controller. | 01-03-2013 |
20130073924 | DATA STORAGE DEVICE AND METHOD TO CORRECT BIT VALUES USING MULTIPLE READ VOLTAGES - A data storage device includes a memory including a plurality of storage elements. The memory is configured to read a group of the storage elements using a first read voltage to obtain a first plurality of bit values. A controller is coupled to the memory. The controller is configured to initiate a first error correction code (ECC) procedure on the first plurality of bit values. In response to the first ECC procedure determining that the first plurality of bit values is not correctable, the controller is further configured to instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values, and to change one or more values of the first plurality of bit values to corresponding values of the second plurality of bit values to generate a first plurality of corrected bit values. | 03-21-2013 |
20130080853 | SYSTEM AND METHOD OF DATA ENCODING - A method includes, after data is stored at a data area of a memory device and error correction code (ECC) data corresponding to the data is stored at an ECC area corresponding to the data area, detecting a triggering condition. In response to detecting the triggering condition, the method also includes storing second ECC data in the ECC area, where the second ECC data includes redundant information for a first portion of the data area and storing third ECC data at the memory device. The third ECC data includes redundant information for a second portion of the data area. | 03-28-2013 |
20130159766 | WEAR LEVELING OF MEMORY DEVICES - A method of managing wear leveling in a data storage device includes determining whether a reliability measurement associated with a first portion of a first nonvolatile memory die satisfies a threshold. The first nonvolatile memory die is included in a plurality of memory dies. The method includes, in response to determining that the reliability measurement associated with the first portion of the first nonvolatile memory die satisfies the threshold, transferring first data from the first portion of the first nonvolatile memory die to a second nonvolatile memory die of the plurality of memory dies. | 06-20-2013 |
20130223151 | SYSTEM AND METHOD OF DETERMINING A PROGRAMMING STEP SIZE FOR A WORD LINE OF A MEMORY - A method includes determining a programming step size for a word line of a memory in a data storage device. The programming step size is determined at least partially based on a count of memory elements of the word line to be programmed to a particular state. | 08-29-2013 |
20130238955 | SYSTEM AND METHOD TO DECODE DATA SUBJECT TO A DISTURB CONDITION - A method includes initiating a first decode operation of data at an error correction code (ECC) hard bit decoder in a data storage device that includes a controller and a memory. The method further includes, in response to the first decode operation indicating that the data is uncorrectable by the first decode operation, identifying one or more bits of the data that correspond to a disturb condition test pattern, changing a value of the one or more identified bits of the data to generate modified data, and initiating a second decode operation at the ECC hard bit decoder using the modified data. | 09-12-2013 |
20130246878 | STATISTICAL DISTRIBUTION BASED VARIABLE-BIT ERROR CORRECTION CODING - A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device. | 09-19-2013 |
20130275651 | SYSTEM AND METHOD OF ADJUSTING A PROGRAMMING STEP SIZE FOR A BLOCK OF A MEMORY - A method includes decreasing a programming step size from a first value to a second value for a block of a memory device. The programming step size is decreased at least partially based on determining that an error count corresponding to the block satisfies a threshold. | 10-17-2013 |
20130275832 | DATA RECOVERY USING ADDITIONAL ERROR CORRECTION CODING DATA - A method in a data storage device including a memory and an error correction coding (ECC) engine. A first ECC page including a data block and first main ECC data is stored to the memory. The first main ECC data is usable by the ECC engine to correct errors in the first ECC page. A second ECC page including first additional ECC data is also stored to the memory. The first additional ECC data is usable by the ECC engine to correct errors in a single sub-block of multiple sub-blocks within the data block. | 10-17-2013 |
20140029336 | SYSTEMS AND METHODS OF UPDATING READ VOLTAGES - A method includes, in a data storage device that includes a non-volatile memory, selecting an updated reference voltage as one of a reference voltage, a first alternate reference voltage and a second alternate reference voltage. The first alternate reference voltage and the second alternate reference voltage are calculated based on the reference voltage and based on a voltage increment. Selection of the updated reference voltage is based on a comparison of error counts, each error count associated with a unique one of the reference voltage, the first alternate reference voltage, and the second alternate reference voltage. The method includes resetting the reference voltage to the updated reference voltage, resetting the voltage increment to a reset voltage increment that is smaller than the voltage increment, and selecting an additional updated reference voltage based on the reset reference voltage and based on the reset voltage increment. | 01-30-2014 |
20140068382 | SYSTEMS AND METHODS TO INITIATE UPDATING OF REFERENCE VOLTAGES - In a data storage device that includes a non-volatile memory, a method includes determining that a current error correction code page count (CEC) is at least as large as a target error correction code page count (TEC). The CEC is a page count of error correction code (ECC) pages of data read from the memory during a time period from a previous time to a particular time using a set of reference voltages. In response to the CEC being at least as large as the TEC, the method includes updating a subset of the set of reference voltages conditioned upon a difference between a current mean error count (CMEC) and a previous mean error count being at least as large as a target mean delta error. The CMEC is based on a count of read errors associated with the ECC pages read during the time period. | 03-06-2014 |
20140173180 | TRACKING READ ACCESSES TO REGIONS OF NON-VOLATILE MEMORY - A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to a read access to a particular region of the non-volatile memory that is tracked by the particular counter. Read accesses to a first region of the non-volatile memory are tracked by a first counter of the set of counters and read accesses to a second region of the non-volatile memory are tracked by a second counter of the set of counters. The method includes, in response to the value of the particular counter indicating that a count of read accesses to the particular region equals or exceeds a first threshold, initiating a remedial action to the particular region of the non-volatile memory. | 06-19-2014 |
20140201580 | SYSTEMS AND METHODS TO UPDATE REFERENCE VOLTAGES IN RESPONSE TO DATA RETENTION IN NON-VOLATILE MEMORY - A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage. The controller is further configured to, at a second time, determine a second count of storage elements having threshold voltages within the voltage range. The controller is further configured to calculate an updated first reference voltage at least partially based on the first reference voltage, the first count, and the second count. | 07-17-2014 |
20140218996 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface. | 08-07-2014 |
20140218997 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface. | 08-07-2014 |
20140219022 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells. | 08-07-2014 |
20140219031 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a first semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory further includes circuitry associated with operation of the multiple memory cells. The apparatus includes a second semiconductor device coupled to the first semiconductor device. The second semiconductor device includes a charge pump, and the 3D memory does not include a charge pump. | 08-07-2014 |
20140269067 | TRACKING ERASE OPERATIONS TO REGIONS OF NON-VOLATILE MEMORY - A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular counter. The method includes, in response to the value of the particular counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory. | 09-18-2014 |
20140269068 | TRACKING ERASE PULSES FOR NON-VOLATILE MEMORY - A data storage device includes a memory and a controller and may perform a method that includes comparing, in the controller, a count of erase pulses to an erase pulse threshold. The count of erase pulses corresponds to a particular region of the non-volatile memory. The method includes, in response to the count of erase pulse satisfying the erase pulse threshold, initiating a remedial action with respect to the particular region of the non-volatile memory. | 09-18-2014 |
20140269069 | TRACKING CELL ERASE COUNTS OF NON-VOLATILE MEMORY - A data storage device includes a memory and a controller and may perform a method that includes updating, in a controller of the data storage device, a value of a particular write/erase (W/E) counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular W/E counter and that includes a storage element that is tracked by a particular cell erase counter of the set of counters. The method includes, in response to the value of the particular W/E counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory at least partially based on the value of the particular cell erase counter. | 09-18-2014 |
20150078078 | APPARATUS AND METHOD OF STORING DATA AT A MULTI-BIT STORAGE ELEMENT - A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes receiving, at the controller, first data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, first dummy data, and second dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The first dummy data and the second dummy data prevent a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states. | 03-19-2015 |
20150078079 | APPARATUS AND METHOD OF STORING DATA AT A MULTI-BIT STORAGE ELEMENT - A storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method performed in the data storage device includes receiving, at the controller, first data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, first dummy data, and second dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The first dummy data and the second dummy data prevent a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states. | 03-19-2015 |
20150081949 | APPARATUS AND METHOD OF USING DUMMY DATA WHILE STORING DATA AT A MULTI-BIT STORAGE ELEMENT - A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes receiving, at the controller, first data and second data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, the second data, and dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The dummy data prevents a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states. | 03-19-2015 |
20150081952 | APPARATUS AND METHOD OF USING DUMMY DATA WHILE STORING DATA AT A MULTI-BIT STORAGE ELEMENT - A storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method performed in the data storage device includes receiving, at the controller, first data and second data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, the second data, and dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The dummy data prevents a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states. | 03-19-2015 |
20150154111 | APPARATUS AND METHOD OF OFFLOADING PROCESSING FROM A DATA STORAGE DEVICE TO A HOST DEVICE - A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes sending an instruction to a host device to cause the host device to perform one or more specified computations. The method further includes receiving a response from the host device. The response is based on execution of the one or more specified computations. | 06-04-2015 |
20150178151 | DATA STORAGE DEVICE DECODER AND METHOD OF OPERATION - A data storage device includes a nonvolatile memory and a controller having a decoder. The nonvolatile memory is operatively coupled to the controller. The nonvolatile memory is configured to store a set of bits. The decoder is configured to receive the set of bits from the memory. The decoder is further configured to perform a decoding operation using the set of bits based on a parity check matrix. The parity check matrix includes a block row. The block row has a first non-zero sub-matrix and a second non-zero sub-matrix that is separated from the first non-zero sub-matrix within the block row by at least a threshold number of null sub-matrices of the block row. | 06-25-2015 |