Patent application number | Description | Published |
20090120584 | COUNTER-BALANCED SUBSTRATE SUPPORT - A semiconductor processing system is described. The system includes a processing chamber having an interior capable of holding an internal chamber pressure below ambient atmospheric pressure. The system also includes a pumping system coupled to the chamber and adapted to remove material from the processing chamber. The system further includes a substrate support pedestal, where the substrate support pedestal is rigidly coupled to a substrate support shaft extending through a wall of the processing chamber. A bracket located outside the processing chamber is provided which is rigidly and sometimes rotatably coupled to the substrate support shaft. A motor coupled to the bracket can be actuated to vertically translate the substrate support pedestal, shaft and bracket from a first position to a second position closer to a processing plate. A piston mounted on an end of the bracket provides a counter-balancing force to a tilting force, where the tilting force is generated by a change in the internal chamber pressure and causes a deflection in the position of the bracket and the substrate support. The counter-balancing force reduces the deflection of the bracket and the substrate support. | 05-14-2009 |
20100006032 | CHAMBER COMPONENTS FOR CVD APPLICATIONS - Apparatus for use with a processing chamber are provided. In one aspect a blocker plate is provided including an annular plate having an inner portion of a first thickness and the annular plate having an aperture pattern including a center portion, a first patterned portion concentrically disposed around the center portion and comprising a first plurality of apertures having a first number of apertures, an second patterned portion concentrically disposed around the first patterned portion and comprising a second plurality of apertures having a second number of apertures greater than the first number of apertures, a perimeter portion concentrically disposed around the second patterned portion, and an outer portion comprising a raised concentric portion disposed on a perimeter of the annular plate. In another aspect, a second, third, and fourth blocker plates are provided. Additionally, a mixing apparatus and a liquid evaporating apparatus for use in a processing chamber are provided. | 01-14-2010 |
20100159711 | PRECURSOR ADDITION TO SILICON OXIDE CVD FOR IMPROVED LOW TEMPERATURE GAPFILL - Methods of depositing silicon oxide layers on substrates involve flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that a uniform silicon oxide growth rate is achieved across the substrate surface. The surface of silicon oxide layers grown according to embodiments may have a reduced roughness when grown with the additive precursor. In other aspects of the disclosure, silicon oxide layers are deposited on a patterned substrate with trenches on the surface by flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that the trenches are filled with a reduced quantity and/or size of voids within the silicon oxide filler material. | 06-24-2010 |
20110129990 | METHOD FOR DOPING NON-PLANAR TRANSISTORS - Methods for doping a non-planar structure by forming a conformal doped silicon glass layer on the non-planar structure are disclosed. A substrate having the non-planar structure formed thereon is positioned in chemical vapor deposition process chamber to deposit a conformal SACVD layer of doped glass (e.g. BSG or PSG). The substrate is then exposed to RTP or laser anneal step to diffuse the dopant into the non-planar structure and the doped glass layer is then removed by etching. | 06-02-2011 |
20110223760 | CONFORMALITY OF OXIDE LAYERS ALONG SIDEWALLS OF DEEP VIAS - A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 μm from a top surface of the nitride layer and an opening of less than about 10 μm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450° C., where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer. | 09-15-2011 |
20120015113 | METHODS FOR FORMING LOW STRESS DIELECTRIC FILMS - A method for forming a multi-layer silicon oxide film on a substrate includes performing a deposition cycle that comprises depositing a silicon oxide layer using a thermal chemical vapor deposition (CVD) process and depositing a silicon oxide layer using a plasma enhanced chemical vapor deposition (PECVD) process. The deposition cycle is repeated a specified number of times to form the multi-layer silicon oxide film comprising a plurality of silicon oxide layers formed using the thermal CVD process and a plurality of silicon oxide layers formed using the PECVD process. Each silicon oxide layer formed using the thermal CVD process is adjacent to at least one silicon oxide layer formed using the PECVD process. | 01-19-2012 |
20120058281 | METHODS FOR FORMING LOW MOISTURE DIELECTRIC FILMS - A method for forming a pre-metal dielectric (PMD) layer or an inter-metal dielectric (IMD) layer over a substrate includes placing the substrate in a chemical vapor deposition (CVD) process chamber and forming a first oxide layer over the substrate in the CVD process chamber. The first oxide layer is formed using a thermal CVD process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The method also includes forming a second oxide layer over the first oxide layer in the CVD process chamber. The second oxide layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The substrate remains in the CVD process chamber during formation of the first oxide layer and the second oxide layer. | 03-08-2012 |
20130252440 | PRETREATMENT AND IMPROVED DIELECTRIC COVERAGE - Methods of conformally depositing silicon oxide layers on patterned substrates are described. The patterned substrates are plasma treated such that subsequently deposited silicon oxide layers may deposit uniformly on walls of deep closed trenches. The technique is particularly useful for through-substrate vias (TSVs) which require especially deep trenches. The trenches may be closed at the bottom and deep to enable through-substrate vias (TSVs) by later removing a portion of the backside substrate (near to the closed end of the trench). The conformal silicon oxide layer thickness on the sidewalls near the bottom of a trench is greater than or about 70% of the conformal silicon oxide layer thickness near the top of the trench in embodiments of the invention. The improved uniformity of the silicon oxide layer enables a subsequently deposited conducting plug to be thicker and offer less electrical resistance. | 09-26-2013 |