| Patent application number | Description | Published |
|---|
| 20080233702 | Method of forming a recess in a semiconductor structure - One embodiment of the present invention relates to a method of processing a semiconductor device. During the method an amorphization implant is performed to amorphize a selected region of a semiconductor structure. The amorphized selected region is then removed by performing a recess etch that is selective thereto. Other methods and systems are also disclosed. | 09-25-2008 |
| 20080268628 | N-TYPE SEMICONDUCTOR COMPONENT WITH IMPROVED DOPANT IMPLANTATION PROFILE AND METHOD OF FORMING SAME - The disclosure relates to a method of forming an n-type doped active area on a semiconductor substrate that presents an improved placement profile. The method comprises the placement of arsenic in the presence of a carbon-containing arsenic diffusion suppressant in order to reduce the diffusion of the arsenic out of the target area during heat-induced annealing. The method may additionally include the placement of an amorphizer, such as germanium, in the target area in order to reduce channeling of the arsenic ions through the crystalline lattice. The method may also include the use of arsenic in addition to another n-type dopant, e.g. phosphorus, in order to offset some of the disadvantages of a pure arsenic dopant. The disclosure also relates to a semiconductor component, e.g. an NMOS transistor, formed in accordance with the described methods. | 10-30-2008 |
| 20080277730 | Semiconductor Device Manufactured Using a Laminated Stress Layer - There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater. | 11-13-2008 |
| 20080308904 | P-DOPED REGION WITH IMPROVED ABRUPTNESS - A method of manufacturing a semiconductor device. The method comprises providing C atoms in a semiconductor substrate. The method also comprises implanting In atoms and p-type dopants into a predefined region of the substrate that is configured to have the carbon atoms. The method further comprises thermally annealing the semiconductor substrate to transform the predefined region into an activated doped region. | 12-18-2008 |
| 20080318387 | Activation of CMOS Source/Drain Extensions by Ultra-High Temperature Anneals - A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate. | 12-25-2008 |
| 20090004803 | MULTI-STAGE IMPLANT TO IMPROVE DEVICE CHARACTERISTICS - One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed. | 01-01-2009 |
| 20090065880 | Semiconductor Device Made by Using a Laser Anneal to Incorporate Stress into a Channel Region - In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal. | 03-12-2009 |
| 20090090990 | FORMATION OF NITROGEN CONTAINING DIELECTRIC LAYERS HAVING AN IMPROVED NITROGEN DISTRIBUTION - Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region. | 04-09-2009 |
| 20090127620 | SEMICONDUCTOR DOPING WITH REDUCED GATE EDGE DIODE LEAKAGE - Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage. The increased concentration of carbon in the source and drain regions may permit heavier doping of the source/drain region, leading to improved gate capacitance. | 05-21-2009 |
| 20090179280 | HIGH THRESHOLD NMOS SOURCE-DRAIN FORMATION WITH As, P AND C TO REDUCE DAMAGE - Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implanatation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·10 | 07-16-2009 |
| 20090184348 | Slim Spacer Implementation to Improve Drive Current - Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor. | 07-23-2009 |
| 20100112764 | Use of Poly Resistor Implant to Dope Poly Gates - A process of fabricating an IC is disclosed in which a polysilicon resistor and a gate region of an MOS transistor are implanted concurrently. The concurrent implantation may be used to reduce steps in the fabrication sequence of the IC. The concurrent implantation may also be used to provide another species of transistor in the IC with enhanced performance. Narrow PMOS transistor gates may be implanted concurrently with p-type polysilicon resistors to increase on-state drive current. PMOS transistor gates over thick gate dielectrics may be implanted concurrently with p-type polysilicon resistors to reduce gate depletion. NMOS transistor gates may be implanted concurrently with n-type polysilicon resistors to reduce gate depletion, and may be implanted concurrently with p-type polysilicon resistors to provide high threshold NMOS transistors in the IC. | 05-06-2010 |
| 20100164003 | MULTIPLE INDIUM IMPLANT METHODS AND DEVICES AND INTEGRATED CIRCUITS THEREFROM - An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×10 | 07-01-2010 |
