Manning, ID
Charles F. Manning, Sandpoint, ID US
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20090267956 | SYSTEMS, METHODS AND ARTICLES FOR VIDEO CAPTURE - Video capture of the output of a computer game is achieved by recording, analyzing and compressing source data output by the computer game, wherein the source data is pre-rasterized graphics data generated by a graphics library. Thus, video capture and subsequent playback of the captured video data involves use of the source data as opposed to raw data resulting from the rasterization of the source data by graphics hardware. | 10-29-2009 |
Christopher Manning, Troy, ID US
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20080204757 | Handheld FT-IR spectrometer - Novel spectrometer arrangements are described. They may employ a resin-based preconcentration system to sample chemical vapors. A field-widened interferometer modulates radiant energy. The signal generated by the interaction of the radiant energy with the sample is detected and processed by a computer. A variety of enhancements to the basic design are described, providing a family of related spectrometer designs. These spectrometers have applications in spectrometry, spectral imaging and metrology. | 08-28-2008 |
20120167698 | PELTIER FREEZE-SHOE SAMPLER TO RECOVER AQUIFER SEDIMENT AND GROUNDWATER - A groundwater sampling tool that includes an elongated hollow coring tube having a proximal end and a distal end for collecting groundwater and sediment; a Peltier element located in close proximity to a wall of the elongated hollow coring tube adapted to freeze groundwater and sediment collected by the elongated hollow coring tube. | 07-05-2012 |
Douglas E. Manning, Kuna, ID US
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20080311754 | LOW TEMPERATURE SACVD PROCESSES FOR PATTERN LOADING APPLICATIONS - A method of improving pattern loading in a deposition of a silicon oxide film is described. The method may include providing a deposition substrate to a deposition chamber, and adjusting a temperature of the deposition substrate to about 250° C. to about 325° C. An ozone containing gas may be introduced to the deposition chamber at a first flow rate of about 1.5 slm to about 3 slm, where the ozone concentration in the gas is about 6% to about 12%, by wt. TEOS may also be introduced to the deposition chamber at a second flow rate of about 2500 mgm to about 4500 mgm. The deposition rate of the silicon oxide film is controlled by a reaction rate of a reaction of the ozone and TEOS at a deposition surface of the substrate. | 12-18-2008 |
H.m. Manning, Eagle, ID US
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20100001267 | NRAM ARRAYS WITH NANOTUBE BLOCKS, NANOTUBE TRACES, AND NANOTUBE PLANES AND METHODS OF MAKING SAME - NRAM arrays with nanotube blocks, traces and planes, and methods of making the same are disclosed. In some embodiments, a nanotube memory array includes a nanotube fabric layer disposed in electrical communication with first and second conductor layers. A memory operation circuit including a circuit for generating and applying a select signal on first and second conductor layers to induce a change in the resistance of the nanotube fabric layer between the first and second conductor layers is provided. At least two adjacent memory cells are formed in at least two selected cross sections of the nanotube fabric and conductor layers such that each memory cell is uniquely addressable and programmable. For each cell, a change in resistance corresponds to a change in an informational state of the memory cell. Some embodiments include bit lines, word lines, and reference lines. In some embodiments, 6F | 01-07-2010 |
H. M. Manning, Eagle, ID US
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20090194839 | NONVOLATILE NANOTUBE DIODES AND NONVOLATILE NANOTUBE BLOCKS AND SYSTEMS USING SAME AND METHODS OF MAKING SAME - A high-density memory array. A plurality of word lines and a plurality of bit lines are arranged to access a plurality of memory cells. Each memory cell includes a first conductive terminal and an article in physical and electrical contact with the first conductive terminal, the article comprising a plurality of nanoscopic particles. A second conductive terminal is in physical and electrical contact with the article. Select circuitry is arranged in electrical communication with a bit line of the plurality of bit lines and one of the first and second conductive terminals. The article has a physical dimension that defines a spacing between the first and second conductive terminals such that the nanotube article is interposed between the first and second conducive terminals. A logical state of each memory cell is selectable by activation only of the bit line and the word line connected to that memory cell. | 08-06-2009 |
20100072459 | NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME - Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate. | 03-25-2010 |
20110057717 | TWO-TERMINAL NANOTUBE DEVICES INCLUDING A NANOTUBE BRIDGE AND METHODS OF MAKING SAME - Nanotube switching devices having nanotube bridges are disclosed. Two-terminal nanotube switches include conductive terminals extending up from a substrate and defining a void in the substrate. Nantoube articles are suspended over the void or form a bottom surface of a void. The nanotube articles are arranged to permanently contact at least a portion of the conductive terminals. An electrical stimulus circuit in communication with the conductive terminals is used to generate and apply selected waveforms to induce a change in resistance of the device between relatively high and low resistance values. Relatively high and relatively low resistance values correspond to states of the device. A single conductive terminal and a interconnect line may be used. The nanotube article may comprise a patterned region of nanotube fabric, having an active region with a relatively high or relatively low resistance value. Methods of making each device are disclosed. | 03-10-2011 |
H.montgomery Manning, Eagle, ID US
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20110291224 | EFFICIENT PITCH MULTIPLICATION PROCESS - Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched. | 12-01-2011 |
20130256827 | EFFICIENT PITCH MULTIPLICATION PROCESS - Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. A photoresist layer is patterned to simultaneously define mask elements in the array, interface and periphery areas. The pattern is transferred to an amorphous carbon layer. Spacers are formed on the sidewalls of the patterned amorphous carbon layer. Protective material is deposited and patterned to expose mask elements in the array region and in parts of the interface or periphery areas. Exposed amorphous carbon is removed, leaving free-standing spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which the substrate is etched. | 10-03-2013 |
H. Montgomery Manning, Kuna, ID US
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20090173982 | METHOD FOR FORMING MEMORY CELL AND DEVICE - A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto. | 07-09-2009 |
20100065941 | INTERMEDIATE SEMICONDUCTOR STRUCTURES - An intermediate semiconductor structure that comprises a substrate and at least one undercut structure formed in the substrate is disclosed. The undercut feature may include a vertical opening having a lateral cavity therein, the vertical opening extending below the lateral cavity. The lateral cavity may include faceted sidewalls. | 03-18-2010 |
Homer M. Manning, Eagle, ID US
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20100052027 | DRAM Layout with Vertical FETS and Method of Formation - DRAM cell arrays having a cell area of about 4 F | 03-04-2010 |
20100117196 | Support For Vertically-Oriented Capacitors During The Formation of a Semiconductor Device - A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during wafer processing. The structure is particularly useful for supporting the bottom plates during removal of a base dielectric layer to expose the outside of the bottom plates to form a double-sided capacitor. The support structure further supports the bottom plates during formation of a cell dielectric layer, a capacitor top plate, and final supporting dielectric. An inventive structure is also described. | 05-13-2010 |
20110254067 | DRAM Layout with Vertical FETS and Method of Formation - DRAM cell arrays having a cell area of about 4F | 10-20-2011 |
20130001663 | DRAM Layout with Vertical FETS and Method of Formation - DRAM cell arrays having a cell area of about 4F | 01-03-2013 |
Jared Manning, Twin Falls, ID US
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20130005035 | METHODS FOR GENERATING T LYMPHOCYTES FROM HEMATOPOIETIC STEM CELLS - This disclosure describes methods for differentiating T cells and NK cells in vitro from hematopoietic stem cells or precursor cells. The technology is directed to methods for the production of selected populations of lymphocytes, such as T cells and NK cells. The availability of such cell populations allows for the complete reconstitution of a depleted, defective or missing lymphocyte population in a patient. | 01-03-2013 |
Kelsey Manning, Preston, ID US
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20090126675 | APPARATUS AND METHOD FOR ENGINE HEAD - An apparatus and method for improving performance in an internal combustion engine includes texturing on an inner surface of at least a portion of an engine head. The texturing may include elongated raised portions extending in one or more directions that may aid in controlling and directing pre-combustion and/or combustion gases in a combustion chamber for a more unified combustion. The result is improved power and/or efficiency. | 05-21-2009 |
Troy Manning, Meridian, ID US
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20100095049 | HOT MEMORY BLOCK TABLE IN A SOLID STATE STORAGE DEVICE - Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the HBLT. If the page table or memory map is already present in the HBLT, the priority location of the page table or memory map is increased to the next priority location. If the page table or memory map is not already stored in the HBLT, the page table or memory map is stored in the HBLT at some priority location, such as the mid-point, and the priority location is incremented with each subsequent access to that page table or memory map. | 04-15-2010 |
20100095084 | TRANSLATION LAYER IN A SOLID STATE STORAGE DEVICE - Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication. | 04-15-2010 |
20100106889 | SOLID STATE DRIVE OPERATION - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event. | 04-29-2010 |
20100268985 | DATA RECOVERY IN A SOLID STATE STORAGE SYSTEM - Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation. | 10-21-2010 |
20130013981 | TEMPORARY MIRRORING, LOGICAL SEGREGATION, AND REDUNDANT PROGRAMMING OR ADDRESSING FOR SOLID STATE DRIVE OPERATION - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event. | 01-10-2013 |
20130080860 | DATA RECOVERY IN A SOLID STATE STORAGE SYSTEM - Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation. | 03-28-2013 |
20140237169 | HOT MEMORY BLOCK TABLE IN A SOLID STATE STORAGE DEVICE - Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the HBLT. If the page table or memory map is already present in the HBLT, the priority location of the page table or memory map is increased to the next priority location. If the page table or memory map is not already stored in the HBLT, the page table or memory map is stored in the HBLT at some priority location, such as the mid-point, and the priority location is incremented with each subsequent access to that page table or memory map. | 08-21-2014 |
20140298090 | DATA RECOVERY IN A SOLID STATE STORAGE SYSTEM - Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation. | 10-02-2014 |
20140365720 | TRANSLATION LAYER IN A SOLID STATE STORAGE DEVICE - Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication. | 12-11-2014 |
Troy A. Manning, Boise, ID US
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20080259696 | DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES - An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time. | 10-23-2008 |
20100097868 | DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES - An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time. | 04-22-2010 |
20120033513 | DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES - An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access. | 02-09-2012 |