| Patent application number | Description | Published |
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| 20080298478 | SCALABLE VLSI ARCHITECTURE FOR K-BEST BREADTH-FIRST DECODING - In some embodiments, a device includes a multiple-input multiple-output (“MIMO”) decoder module coupled to a first log-likelihood-ratio (“LLR”) computing unit. The decoder module includes at least one processing unit and at least one sorting unit. The decoder module preferably uses a K-best breadth-first search method to decode data from MIMO sources. In some embodiments, a method includes receiving data representing a vector of receive signal samples detected by multiple receive transceivers. The method further includes performing a K-best breadth-first search on the data to obtain an estimated constellation point. The method further includes providing a user data stream based at least in part on the estimated constellation point. | 12-04-2008 |
| 20080298493 | N-CANDIDATE DEPTH-FIRST DECODING - The problem outlined above may at least in part be addressed by N-Candidate Depth-First Decoding methods and systems that employ such methods. In some embodiments, the method includes receiving data representing a vector of receive signals detected by multiple receive transceivers; performing an N-candidate, depth-first search on the data to obtain an estimated constellation point; and providing a user data stream based at least in part on the estimated constellation point. In some embodiments the system includes a multiple-input multiple-output decoder. The decoder is configured to perform an N-candidate, depth-first search as part of converting a receive signal into a data stream. | 12-04-2008 |
| 20090052433 | METHOD OF SYNCHRONIZATION FOR PACKET BASED, OFDM WIRELESS SYSTEMS WITH MULTIPLE RECEIVE CHAINS - A system for synchronizing a wireless receiver is provided. The system includes a first antenna and a second antenna to receive independent wireless signals containing different combination of data packets. The system includes one or more analyzer components operable to determine correlation metrics based on at least a portion of the first received signal and a portion of the second received signal. The system further includes a synchronization component operable to use the correlation metrics to determine a preferred correlation metric for synchronization by the wireless receiver of the first and second received signals to decode the data packet. A method for synchronizing a receiver of two wireless signals is also provided. | 02-26-2009 |
| 20090089556 | High-Speed Add-Compare-Select (ACS) Circuit - A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay. | 04-02-2009 |
| 20090110126 | REDUCED COMPLEXITY VITERBI DECODER - A Viterbi decoder includes a branch metric unit, an add-compare select unit coupled to the branch metric unit, and a trace-back unit coupled to the add-compare select unit. The branch metric unit includes a branch metric computation unit coupled to a thresholder unit. The branch metric computation unit is configured to compute a branch metric. The thresholder unit is configured to compare the branch metric with a threshold value. If the branch metric is greater than the threshold value, the thresholder unit is configured to forward the threshold value to the add-compare select and not forward the branch metric to the add-compare select unit. Implementing such a branch metric ceiling allows for a predictable reduction in the significant bits of calculations in the Viterbi decoder, which allows for reduction of complexity via elimination of gates and storage elements. | 04-30-2009 |
| 20100034321 | Sharing Logic Circuitry for a Maximum Likelihood MIMO Decoder and a Viterbi Decoder - A receiver system for receiving and decoding modulated communications signals in a multiple-input, multiple-output (MIMO) environment, where the signals are modulated according to Orthogonal Frequency Division Modulation (OFDM). The receiver system includes shared decoder logic circuitry that executes a maximum-likelihood (ML) estimation algorithm in deriving the signals transmitted from the multiple transmitting antennae, as those signals were received over all of the receiving antennae. For a control channel portion of the data frame, the shared decoder logic circuitry applies Viterbi decoding to the transmitted datastreams estimated by the ML estimation algorithm. This sharing of decoder logic reduces the integrated circuit chip area, and also power dissipation, otherwise required in performing these complex decoding functions. | 02-11-2010 |
| 20100034324 | REDUCED COMPLEXITY VITERBI DECODING - A system includes a Viterbi decoder. The Viterbi decoder includes add compare select logic. The add compare select logic determines path metrics for an encoded signal. The add compare select logic also is shared to determine a best state by which trace-back procedure gets started, resulting in hardware saving. | 02-11-2010 |
| 20100034325 | LOW-POWER PREDECODING BASED VITERBI DECODING - In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value. | 02-11-2010 |
| 20100115386 | Scalable Folded Decoder Architecture for Low Density Parity Check Codes - A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1. | 05-06-2010 |
| 20100122142 | Scalable Decoder Architecture for Low Density Parity Check Codes - A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W>=1. The architecture does not require duplication of extrinsic memory which greatly reduces decoder complexity. The size of the memory is also independent of sub-matrix degree which makes the decoder scalable for large W values. | 05-13-2010 |
| 20110055643 | RECEIVER POWER SAVING VIA BLOCK CODE FAILURE DETECTION - A communication system includes a receiver configured to receive a packet that contains plural codewords, and a codeword failure detector cooperatively operable with the receiver. The codeword failure detector can be configured to detect a codeword failure in at least one codeword of the plural codewords as it is being received by the receiver, and to terminate reception at the receiver, when the codeword failure is detected before the end of the packet, to put the receiver into a power save mode for a duration of a remainder of the packet that contains the at least one codeword. | 03-03-2011 |
| 20110055668 | METHOD, DEVICE, AND DIGITAL CIRCUITY FOR PROVIDING A CLOSED-FORM SOLUTION TO A SCALED ERROR LOCATOR POLYNOMIAL USED IN BCH DECODING - A method of determining positions of one or more error bits is disclosed. The method includes receiving a BCH codeword at input circuitry of a decoder device, establishing a threshold number of correctable bits, and determining from the received BCH codeword and a root of an encoder polynomial, a value of each of one or more syndromes. The number of the one or more syndromes is twice a maximum number of correctable bits in the received BCH codeword. When the maximum number of correctable bits in the received BCH codeword is less than the threshold number of correctable bits, the value of each coefficient in a scaled error locator polynomial is determined by performing a non-iterative, closed-form solution on the scaled error locator polynomial. The scaled error locator polynomial is an original error locator polynomial scaled by a constant scale factor. The constant scale factor is determined according to the value of each of the one or more syndromes. Having determined the value of each coefficient in the scaled error locator polynomial, one or more roots of the scaled error locator polynomial are obtained. Each of the one or more roots indicates a position of an error bit. A BCH decoder device that can implement the method and a digital circuit that preserves operations implementing the method are also disclosed. | 03-03-2011 |
