Patent application number | Description | Published |
20090132972 | METHOD AND APPARATUS FOR DETERMINING ELECTRO-MIGRATION IN INTEGRATED CIRCUIT DESIGNS - A method and apparatus for determining electro-migration (EM) in integrated circuit designs is disclosed. In one embodiment, a method includes pre-characterizing an output current waveform for a logic cell of the circuit at selected load and input slew points, estimating an effective load and operating slews at a chip level of the circuit and directly generating an equivalent current source waveform at output, evaluating current densities through a metal segment of the circuit using a fast solver, parametrically representing process variations and a netlist to parametrically model the interconnect variations of the circuit, and determining current densities for selected yield numbers using a parametrically generated current source on an interconnect network, wherein calculated results statistically predict a point of current density less than 9−σ a through any metal segment in the parametrically modeled circuit. The method may further include comparing selected current densities with predetermined EM guidelines. | 05-21-2009 |
20090187868 | DESIGN OF INTEGRATED CIRCUITS LESS SUSCEPTIBLE TO DEGRADATIONS IN TRANSISTORS CAUSED DUE TO OPERATIONAL STRESS - According to an aspect of the present invention, statistical timing analysis is applied with respect to a stress degradation that occurs in fabricated integrated circuits (IC) when used for a long duration. The circuit design may be suitably modified to account for the degradations (e.g., those caused by NBTI and CHC for transistors, those caused due to electromigration in case of interconnects). As a result, the fabricated ICs may be less susceptible to such degradations. The features are extended to model complex circuit blocks and also account for different degrees of stress that different circuit blocks are subjected to, in a same age of operation. | 07-23-2009 |
20120167031 | METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE BASED ON LEAKAGE CURRENT ESTIMATION - A method of designing a semiconductor device includes preparing a first design for a semiconductor device and estimating leakage current for the first design. The method also includes determining a leakage current cumulative distribution function (CDF) for the first design. The method further includes preparing a second design for the semiconductor device based on determination of the leakage current CDF for the first design. Further, the method includes estimating leakage current for the second design. The method also includes determining a leakage current CDF for the second design in accordance to the determination of the leakage current CDF for the first design. Moreover, the method includes selecting one of the first design and the second design based on a comparison of the leakage current CDF for the first design and the leakage CDF for the second design. | 06-28-2012 |
Patent application number | Description | Published |
20120142931 | Purification of montelukast using simulated moving bed - This invention concerns generally with a process for purifying crude pharmaceutical compositions, wherein the crude pharmaceutical composition comprises a sodium salt of Montelukast | 06-07-2012 |
20120184774 | PROCESS FOR THE PREPARATION OF PHARMACEUTICALLY ACCEPTABLE SALTS OF RACEMIC MILNACIPRAN AND ITS OPTICAL ENANTIOMERS THEREOF - The present invention relates to an improved process for the preparation of pharmaceutically acceptable salts of milnacipran by mutual acid radical exchange. | 07-19-2012 |
20120289744 | PROCESS FOR PREPARING OPTICALLY PURE MILNACIPRAN AND ITS PHARMACEUTICALLY ACCEPTABLE SALTS - The present invention relates to an improved and commercially, viable process for the resolution of racemic cis milnacipran of formula I and its pharmaceutically acceptable salts of formula II. The present invention comprises using racemic cis milnacipran or its pharmaceutically acceptable salts as starting material, a low cost and commercially available resolving agent of formula III and industrially safe and economically low cost material such as water as a solvent. The said process results into optical isomers of racemic cis milnacipran having excellent optical purity without involving multiple crystallization steps. The present invention also comprises the concept of green chemistry as the invention works well with water as a solvent thereby minimizing the use of any other solvent. (Formular I and II should be inserted here) Wherein X is anion selected from Cl, Br, I, HSO | 11-15-2012 |
20130053579 | PROCESS FOR THE PREPARATION OF N-METHYL-O-ARYLOXY PROPANAMINE DERIVATIVES AND PHARMACEUTICALLY ACCEPTABLE SALT THEREOF - A process for the preparation on N-methyl-aryloxy-propanamine derivatives of the formula I and salts thereof. The invention also relates to the preparation and use novel intermediate of the formula XII. The invention also relates to the process of further conversion of novel intermediate into N-methyl-aryloxy propanamine derivatives and salts thereof. | 02-28-2013 |
Patent application number | Description | Published |
20090237121 | Correlated double sampling technique - A sampling circuit according to correlated double sampling to generate a difference of two voltages at a sampling node, with the second voltage representing the sum of an input signal and an offset, and the first voltage representing the offset alone. In an embodiment, a first capacitor is charged to the first voltage in a first phase. A second capacitor is then charged to the second voltage in a second phase. In a third phase, the first capacitor is coupled to the input terminal of the amplifier and the second capacitor is coupled between the input and output terminals of the amplifier to cause the amplifier to generate the difference of the first and second voltages. The first capacitor has a capacitance much less than the second capacitor, thereby minimizing the noise power at the output of the amplifier. | 09-24-2009 |
20110133970 | MULTIPATH AMPLIFIER - Because of variations in open loop gain and bandwidth in successive approximate register (SAR) analog-to-digital converters (ADCs), designing amplifiers with the desired characteristics is difficult. Here, a multipath amplifier is provided that accounts for the variations in open loop gain and bandwidth. Preferably, a number of cascaded amplifiers are provided that can auto-zero to account for offset voltages so as to allow the multipath amplifier to be stable over the desired open loop gains and bandwidths. | 06-09-2011 |
20110304492 | MULTI-CHANNEL SAR ADC - For high voltage applications, multi-channel successive approximation register (SAR) analog-to-digital converters (ADCs) are often plagued with numerous problems that are generally associated with parasitics (which are present in high voltage components). Here, a different architecture is provided where the sampling capacitors are separated from conversion capacitors so as to have low voltage components in the conversion path. Additionally, to improve the acquisition time and reduced total harmonic distortion (THD) multiple channels can use the same sampling capacitors. | 12-15-2011 |
20150372691 | SYSTEM AND METHOD FOR MULTI CHANNEL SAMPLING SAR ADC - A device includes a SAR, a comparator, a DAC and a multichannel passive S/H component. The multichannel passive S/H component is able to sample and hold a plurality of analog voltages in parallel. The multichannel passive S/H component is further able to serially feed the plurality of sampled and held analog voltages to the SAR, comparator and DAC, such that each analog voltage is serially converted to a digital representation. | 12-24-2015 |
Patent application number | Description | Published |
20100131744 | METHOD AND SYSTEM OF A PROCESSOR-AGNOSTIC ENCODED DEBUG-ARCHITECTURE IN A PIPELINED ENVIRONMENT - A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having combinations of the event and other events occurring simultaneously in the processor, capturing an output data of observed ones of the event and other events, and applying the matrix to generate an encoded debug data of the output data. The method may also include determining which of the combinations are valid based on an architecture of the processor. The event may be a trace-worthy event whose output value cannot be reliably predicted in an executable file in the data processing system and/or a sync event that is specified by a user of the data processing system. | 05-27-2010 |
20120011404 | METHOD AND SYSTEM OF A PROCESSOR-AGNOSTIC ENCODED DEBUG-ARCHITECTURE IN A PIPELINED ENVIRONMENT - A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having combinations of the event and other events occurring simultaneously in the processor, capturing an output data of observed ones of the event and other events, and applying the matrix to generate an encoded debug data of the output data. The method may also include determining which of the combinations are valid based on an architecture of the processor. The event may be a trace-worthy event whose output value cannot be reliably predicted in an executable file in the data processing system and/or a sync event that is specified by a user of the data processing system. | 01-12-2012 |
20120216080 | EMBEDDING STALL AND EVENT TRACE PROFILING DATA IN THE TIMING STREAM - EXTENDED TIMING TRACE CIRCUITS, PROCESSES, AND SYSTEMS - An electronic tracing process includes packing both stall ( | 08-23-2012 |
20150149833 | EMBEDDING STALL AND EVENT TRACE PROFILING DATA IN THE TIMING STREAM - EXTENDED TIMING TRACE CIRCUITS, PROCESSES, AND SYSTEMS - An electronic tracing process includes packing both stall ( | 05-28-2015 |
20150271494 | LOW POWER ULTRA-HD VIDEO HARDWARE ENGINE - A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N. | 09-24-2015 |
20150271512 | DYNAMIC FRAME PADDING IN A VIDEO HARDWARE ENGINE - A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame. | 09-24-2015 |
20150296212 | Processor Instructions for Accelerating Video Coding - A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding. | 10-15-2015 |
20150365696 | OPTICAL FLOW DETERMINATION USING PYRAMIDAL BLOCK MATCHING - An image processing system includes a processor and optical flow determination logic. The optical flow determination logic is to quantify relative motion of a feature present in a first frame of video and a second frame of video with respect to the two frames of video. The optical flow determination logic configures the processor to convert each of the frames of video into a hierarchical image pyramid. The image pyramid comprises a plurality of image levels. Image resolution is reduced at each higher one of the image levels. For each image level and for each pixel in the first frame, the processor is configured to establish an initial estimate of a location of the pixel in the second frame and to apply a plurality of sequential searches, starting from the initial estimate, that establish refined estimates of the location of the pixel in the second frame. | 12-17-2015 |
20160062869 | EMBEDDING STALL AND EVENT TRACE PROFILING DATA IN THE TIMING STREAM - EXTENDED TIMING TRACE CIRCUITS, PROCESSES, AND SYSTEMS - An electronic tracing process includes packing both stall ( | 03-03-2016 |
20160124651 | METHOD FOR PERFORMING RANDOM READ ACCESS TO A BLOCK OF DATA USING PARALLEL LUT READ INSTRUCTION IN VECTOR PROCESSORS - This invention deals with the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory. | 05-05-2016 |
20160125257 | Optimized Fast Feature Detection for Vector Processors - This invention enables effective corner detection of pixels of an image using the FAST algorithm using a vector SIMD processor. This invention loads an 8×8 pixel block that includes four 7×7 pixel blocks including the 16 peripheral pixels to be tested for each of four center pixels. This invention rearranges the 64 pixels of the 8×8 block to form a 16 element array for each center pixel preferably using a vector permutation instruction. This invention uses vector SIMD subtraction and compare and vector SIMD addition and compare to make the FAST algorithm comparisons. The N consecutive pixels determinations of the FAST algorithm are made from the results of plural shift and AND operations. The corresponding center pixel is marked a corner or not a corner dependent upon of the results of plural shift and AND operations. | 05-05-2016 |
20160125263 | METHOD TO COMPUTE SLIDING WINDOW BLOCK SUM USING INSTRUCTION BASED SELECTIVE HORIZONTAL ADDITION IN VECTOR PROCESSOR - This invention forms a block sum of picture elements employing a vector dot product instruction to sum packed picture elements and the mask producing a vector of masked horizontal picture element. The block sum is formed from plural horizontal sums via vector single instruction multiple data (SIMD) addition. | 05-05-2016 |
Patent application number | Description | Published |
20090275647 | TAXANE DERIVATIVE COMPOSITION - A stable, absolutely ethanol free composition of docetaxel that prevents alcoholic intoxication or anaphylactic shock. The composition can be in the form of a stable injectable composition that includes a taxane derivative, wherein the composition includes a mixture of docetaxel, one or more stabilizer, one or more surfactant, or more co-solvent and water for injection wherein the composition is absolutely free of ethanol. | 11-05-2009 |
20100248376 | IN-VITRO METHOD FOR TESTING BIOEQUIVALENCE OF IRON-SUCROSE FORMULATION - The present disclosure relates to an in vitro method for measuring the T | 09-30-2010 |
20100267824 | STABLE OXALIPLATIN COMPOSITION FOR PARENTERAL ADMINISTRATION - The present invention relates to a stable parenteral composition of oxaliplatin having pH range in between 3 to 4.5, which comprises of a solution of oxaliplatin in water wherein the said pH is attained by sparging of carbon dioxide in the composition. Further, a method for the preparation of oxaliplatin composition of the present invention is also disclosed. | 10-21-2010 |
20110177137 | NOVEL DOSAGE FORM OF PALIPERIDONE AND PROCESS FOR PREPARING THE SAME - The present invention relates to an extended release composition of paliperidone for oral administration comprising paliperidone and at least one matrixing agent. The said extended release composition maintains desired therapeutic drug effect over a prolonged period of time and thereby reduces the side effects resulting due to excess drug blood plasma concentration. Further, the invention also relates to process for the preparation of an extended release oral composition of paliperidone. | 07-21-2011 |
20120252835 | STABLE TEMSIROLIMUS COMPOSITION AND PROCESS OF PREPARING SAME - The present disclosure describes a stable composition of Temsirolimus for parenteral administration. The composition includes BHA or BHT as anti-oxidants and alcoholic solvent. The pH of the composition is below 5.0. The composition also can include a chelating agent and/or a surfactant. A method of producing the composition is also described. | 10-04-2012 |
20130303464 | STABLE READY-TO-USE CETRORELIX INJECTION - The present invention discloses a stable ready-to-use aqueous pharmaceutical preparation containing Cetrorelix or its pharmaceutically acceptable salt, wherein the preparation does not contain any surfactant. Further, the present invention discloses process for the preparation of said stable ready-to-use aqueous pharmaceutical preparation. | 11-14-2013 |
20150328165 | PHARMACEUTICALLY ACCEPTABLE DOSAGE FORM COMPRISING RELEASE OF MULTIPLE DRUGS FROM SINGLE ORAL DOSAGE FORM - Present invention relates to a pharmaceutically acceptable dosage form covering multiple drug in one capsule wherein one of these drugs is tetracycline. In the present invention current dosage form tetracycline is in tablet form filled in the capsule. Additionally this dosage may also comprise multiple release of drug. | 11-19-2015 |
Patent application number | Description | Published |
20140111258 | Power-on-Reset and Supply Brown Out Detection Circuit with Programmability - A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points and hysteresis voltage is presented. The PoR circuit includes a CMOS circuit with asymmetric rise and fall delays for monitoring wideband supply voltage transients including supply brown out. Being a non-bandgap and non-comparator based circuit, it consumes a very small power and Si area. | 04-24-2014 |
20140368176 | GENERATING A ROOT OF AN OPEN-LOOP FREQENCY RESPONSE THAT TRACKS AN OPPOSITE ROOT OF THE FREQUENCY RESPONSE - In an embodiment, an electronic includes a feedback-coupled circuit stage and a compensation circuit stage. The feedback-coupled stage is configured to drive a load, and the compensation stage is coupled to the feedback-coupled stage such that a combination of the compensation and feedback-coupled stages has a frequency response including a first root and an opposite second root that depend on the load. For example, an embodiment of such an electronic circuit may be a low-dropout (LDO) voltage regulator that lacks a large output capacitance for forming a dominant pole to stabilize the regulator. The regulator includes a feedback-coupled stage that generates and regulates an output voltage, and includes a compensation stage that is designed such that the frequency response of the regulator includes a zero that tracks a non-dominant output pole of the regulator so that the output pole does not adversely affect the stability of the regulator. | 12-18-2014 |
20150236689 | Power-on-Reset and Supply Brown Out Detection Circuit with Programmability - A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points and hysteresis voltage is presented. The PoR circuit includes a CMOS circuit with asymmetric rise and fall delays for monitoring wideband supply voltage transients including supply brown out. Being a non-bandgap and non-comparator based circuit, it consumes a very small power and Si area. | 08-20-2015 |
Patent application number | Description | Published |
20090128104 | FULLY INTEGRATED ON-CHIP LOW DROPOUT VOLTAGE REGULATOR - A low dropout voltage regulator (LDO) includes a bias voltage generator, a differential error amplifier, an output driver, a controlled active load, a Double Ended Cascode Miller compensation block. The bias voltage generator produces a plurality of bias voltages. The differential error amplifier produces a differential output voltage based on the difference between a reference voltage and a function of the output voltage. The input terminal of the output driver is coupled to one output of the differential error amplifier. The substrate terminal of the output driver is capacitively coupled to the output node and resistively coupled to the input supply node. The controlled active load is coupled to the output of the output driver, and its control terminal is coupled to a function of the second output of the differential error amplifier. The inputs of the Double Ended Cascode Miller compensation block are capacitively coupled to the output node and its output is coupled to the input terminal of the output driver. | 05-21-2009 |
20090289610 | LOW DROPOUT REGULATOR - The present invention provides a low dropout (LDO) regulator with a stability compensation circuit. A “zero frequency” tracking as well as “non-dominant parasitic poles' frequency reshaping” are performed to achieve a good phase margin for the LDO by means of the compensation circuit. In this compensation method neither a large load capacitor nor its equivalent series resistance is needed to stabilize a regulator. LDO regulators, in system on chip application, having load capacitors in the range of few nano-Farads to few hundreds of nano-Farads can be efficiently compensated with this compensation method. A dominant pole for the regulator is realized at an internal node and the second pole at an output node of the regulator is tracked with a variable capacitor generated zero over a range of load current to cancel the effect of each other. A third pole of the system is pushed out above the unity gain frequency of the open loop transfer function with the help of the frequency compensation circuit. The compensation technique is very effective in realizing a low power, low-load-capacitor LDO desirable for system on chip applications. | 11-26-2009 |
20140111258 | Power-on-Reset and Supply Brown Out Detection Circuit with Programmability - A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points and hysteresis voltage is presented. The PoR circuit includes a CMOS circuit with asymmetric rise and fall delays for monitoring wideband supply voltage transients including supply brown out. Being a non-bandgap and non-comparator based circuit, it consumes a very small power and Si area. | 04-24-2014 |
20140368176 | GENERATING A ROOT OF AN OPEN-LOOP FREQENCY RESPONSE THAT TRACKS AN OPPOSITE ROOT OF THE FREQUENCY RESPONSE - In an embodiment, an electronic includes a feedback-coupled circuit stage and a compensation circuit stage. The feedback-coupled stage is configured to drive a load, and the compensation stage is coupled to the feedback-coupled stage such that a combination of the compensation and feedback-coupled stages has a frequency response including a first root and an opposite second root that depend on the load. For example, an embodiment of such an electronic circuit may be a low-dropout (LDO) voltage regulator that lacks a large output capacitance for forming a dominant pole to stabilize the regulator. The regulator includes a feedback-coupled stage that generates and regulates an output voltage, and includes a compensation stage that is designed such that the frequency response of the regulator includes a zero that tracks a non-dominant output pole of the regulator so that the output pole does not adversely affect the stability of the regulator. | 12-18-2014 |
20150236689 | Power-on-Reset and Supply Brown Out Detection Circuit with Programmability - A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points and hysteresis voltage is presented. The PoR circuit includes a CMOS circuit with asymmetric rise and fall delays for monitoring wideband supply voltage transients including supply brown out. Being a non-bandgap and non-comparator based circuit, it consumes a very small power and Si area. | 08-20-2015 |
Patent application number | Description | Published |
20150280898 | OVERSAMPLING CDR WHICH COMPENSATES FREQUENCY DIFFERENCE WITHOUT ELASTICITY BUFFER - A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter. | 10-01-2015 |
20160119117 | OVERSAMPLING CDR WHICH COMPENSATES FREQUENCY DIFFERENCE WITHOUT ELASTICITY BUFFER - A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter. | 04-28-2016 |
Patent application number | Description | Published |
20130261833 | ARCHITECTURE FOR ENERGY MANAGEMENT OF MULTI CUSTOMER MULTI TIME ZONE DISTRIBUTED FACILITIES - A system and method for energy management for multi customer multi time zone distributed facilities are disclosed. In one embodiment, data associated with the energy management of the multi customer distributed facilities located in different time zones is obtained based on associated energy models by a data acquisition/integration layer. Further, the obtained data for energy management of the multi customer distributed facilities is transformed by a data management layer. Furthermore, control commands are generated using the transformed data and associated one or more pre-defined thresholds and set-points by an energy transaction layer. Also, energy of the multi customer distributed facilities is substantially simultaneously managed using the generated control commands by the energy transaction layer. | 10-03-2013 |
20150120073 | SYSTEM AND METHOD FOR MODELING OF TARGET INFRASTRUCTURE FOR ENERGY MANAGEMENT IN DISTRIBUTED-FACILITIES - This disclosure relates to modeling of target infrastructure for energy management in distributed-facilities. In one embodiment, an energy management modeling method is disclosed, comprising: obtaining customer facility information and a customer business type; obtaining energy management industry standard information related to the customer business type; generating a baseline customer knowledge base, based on the obtained energy management industry standard information; obtaining facility historical operational information and operational policy information; generating a first energy operational model using the customer facility information, the baseline customer knowledge base, the facility historical operational information, and the operational policy information; generating a mapping of energy sources to asset systems, using the first energy operational model; generating an optimized energy operational model using the mapping of the energy sources to asset systems, wherein the optimized energy operational model utilizes an objective function of cost, energy consumption, and emission; and providing the optimized energy operational model. | 04-30-2015 |
Patent application number | Description | Published |
20130023710 | FCC CATALYST ADDITIVE AND A METHOD FOR ITS PREPARATION - The present invention relates to a Fluid Catalytic Cracking (FCC) additive preparation process and composition, which has high efficiency in the production of light olefins C2, C3 and C4 hydrocarbons, specifically propylene. The present invention discloses the stabilization of medium pore zeolite specifically ZSM-5 using optimum phosphate salts at a pH in the range 7-9 with synergetic combination of silica rich binder to produce FCC additive having excellent stability under severe hydrothermal conditions. | 01-24-2013 |
20130306906 | ADIABATIC REGENERATION OF SULFUR CAPTURING ADSORBENTS - The present invention provides a process for regeneration of the sulfur capturing spent adsorbents after sulfur capturing using a hydrolyzing agent under adiabatic conditions. In accordance with the process of the present invention hydrolyzing agent is introduced to the spent adsorbent in a controlled manner such that the exothermic heat generated within the adsorbent bed does not rise above the predetermined temperature limit. | 11-21-2013 |
20130313159 | PROCESS FOR IMPROVING AROMATICITY OF HEAVY AROMATIC HYDROCARBONS - A process for producing paraffin extracted clarified slurry oil (raffinate) with improved aromaticity from the feed stock such as clarified slurry oil (CSO) is provided. The obtained paraffin extracted clarified slurry oil with improved aromaticity is suitable for a variety of industrial applications. For example, it can be used as a valuable feedstock for producing carbon black. | 11-28-2013 |
20140116923 | PROCESS AND COMPOSITION OF CATALYST/ADDITIVE FOR REDUCING FUEL GAS YIELD IN FLUID CATALYTIC CRACKING (FCC) PROCESS - The present invention relates to a catalyst for Fluid Catalytic Cracking (FCC) which contains a combination of a FCC catalyst component and an additive component with certain physical properties attributed therein. The present invention is also directed to provide methods for the preparation of the catalyst for FCC. The admixture of the FCC catalyst component and additive component is used in cracking of hydrocarbon feedstock containing hydrocarbons of higher molecular weight and higher boiling point and/or olefin gasoline naphtha feedstock for producing lower yield of fuel gas with out affecting the conversion and yield of general cracking products such as gasoline, propylene and C | 05-01-2014 |
20140194657 | System and Method for Preparing Hydrocarbon Blend from Multiple Component Streams - A computer implemented blend control system and method for preparation of a hydrocarbon blend from a plurality of components drawn from respective component tanks have been disclosed. The system, in accordance with the present disclosure includes at least one sensing and analyzing means adapted to sense and analyze a first attribute of at least one of the components for obtaining first attribute data. The system further includes, at least one optimizing means having a data storage means for storing attribute based model data. The optimizing means receives the first attribute data and transmits the received first attribute data to a comparator means which computes an optimized proportion data between each of the component streams to enable selective drawing of each of the component streams in accordance with the optimized proportion data for preparing the hydrocarbon blend. | 07-10-2014 |
20140195055 | Computer Implemented Blend Control System and Method for Preparation of a Hydrocarbon Blend - A computer implemented blend control system and method for preparation of a hydrocarbon blend from a plurality of component streams have been disclosed. The system includes a product tank for receiving a mixture comprising the plurality of component streams. The system further includes a sensing and analyzing means adapted to sense and analyze a first attribute of the received mixture for obtaining a first attribute data. The system further includes an optimizing means which stores the attribute based model data, receives the first attribute data and compares the received first attribute data with the attribute based model data to compute an optimized proportion data, based on which the component streams are selectively drawn into the product tank for preparing the hydrocarbon blend. | 07-10-2014 |
20140357912 | PROCESS FOR CATALYTIC CONVERSION OF LOW VALUE HYDROCARBON STREAMS TO LIGHT OLEFINS - A process for catalytic conversion of low value hydrocarbon streams to light olefins in comparatively higher yields is disclosed. Propylene is obtained in amounts higher than 20 wt. % and ethylene higher than 6 wt. %. The process is carried out in a preheated cracking reactor having a single riser and circulating an FCC catalyst. The riser is divided into three temperature zones in which different hydrocarbon feeds are introduced. An oxygenate feed is introduced in the operative top zone in the riser. Heat for the endothermic cracking is obtained by the exothermic reaction of converting the oxygenate feed into gas and/or from a regenerator in which the spent FCC catalyst is burnt. | 12-04-2014 |
20150361362 | A PROCESS FOR CATALYTIC GASIFICATION OF CARBONACEOUS FEEDSTOCK - An improved process for the catalytic gasification of a carbonaceous feedstock in a dual fluidized bed reactor for producing synthesis gas is disclosed. The disclosure uses γ-alumina as a catalyst support iand heat carrier in the gasification zone ( | 12-17-2015 |