| Patent application number | Description | Published |
|---|
| 20090093625 | APPARATUS FOR AND METHOD OF SYNTHESIZING BIOPOLYMER AND METHOD OF RECOVERING REAGENT FOR SYNTHESIZING BIOPOLYMER - An apparatus for synthesizing a biopolymer includes a reaction chamber, an outlet tube connected to the reaction chamber, a plurality of recovery tanks connected to the outlet tube, and a plurality of recovery valves configured to open or block the passageway between the outlet tube and each of the recovery tanks. | 04-09-2009 |
| 20090111168 | BIOCHIP AND METHOD OF FABRICATION - A biochip and method of fabricating the same are provided. The biochip can include a substrate, a capping layer pattern partially covering a top surface of the substrate, and a plurality of probes coupled to the top surface of the substrate exposed by the capping layer pattern. | 04-30-2009 |
| 20090111169 | BIOCHIP AND METHOD OF FABRICATION - A biochip and method of fabricating the same are provided. The biochip can include a substrate, a plurality of active pads formed on the substrate, each of the plurality of active pads having a surface roughness and being patterned so as to produce photonic crystals, and a plurality of probes directly or indirectly coupled with at least some of the plurality of active pads. | 04-30-2009 |
| 20090117645 | Biochips and methods of fabricating the same - Biochips for analyzing components of a biological sample using probes and methods of fabricating the same are provided. In some embodiments, a biochip includes a substrate, a plurality of probes immobilized on a top surface of the substrate, and a capping layer formed on a bottom surface of the substrate. | 05-07-2009 |
| 20090162998 | Methods of Manufacturing Memory Units, and Methods of Manufacturing Semiconductor Devices - Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided. | 06-25-2009 |
| 20090209071 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - First nanowires and second nanowires are alternately disposed and spaced apart on a first substrate in a second direction that is parallel to an adjacent major surface of the first substrate. Each of the first and second nanowires extends in a first direction that is perpendicular to the second direction, and the first and second nanowires are doped with first and second conductive types, respectively. A plurality of gate lines are formed that are at least partially disposed within the first substrate, that are spaced apart in a third direction, that extend in a fourth direction that is perpendicular to the third direction, and that partially enclose the first and second nanowires | 08-20-2009 |
| 20100190303 | Semiconductor device having sufficient process margin and method of forming same - According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed. | 07-29-2010 |
| 20100314600 | Memory Units and Related Semiconductor Devices Including Nanowires - Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided. | 12-16-2010 |
| 20110156159 | Semiconductor device having sufficient process margin and method of forming same - According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed. | 06-30-2011 |
