Patent application number | Description | Published |
20100213526 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof. | 08-26-2010 |
20110057322 | CARBON NANOTUBE INTERCONNECT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a carbon nanotube interconnect includes a first interconnection layer, an interlayer dielectric film, a second interconnection layer, a contact hole, a plurality of carbon nanotubes and a film. The interlayer dielectric film is formed on the first interconnection layer. The second interconnection layer is formed on the interlayer dielectric film. The contact hole is formed in the interlayer dielectric film between the first interconnection layer and the second interconnection layer. The carbon nanotubes are formed in the contact hole. The carbon nanotubes have a first end connected to the first interconnection layer and a second end connected to the second interconnection layer. The film is formed between the interlayer dielectric film and the second interconnection layer. The film has a portion filled between the second ends of the carbon nanotubes. | 03-10-2011 |
20110233779 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes an interlayer insulation film provided on a substrate including a Cu wiring, a via hole formed in the interlayer insulation film on the Cu wiring, a first metal film selectively formed on the Cu wiring in the via hole, functioning as a barrier to the Cu wiring, and functioning as a promoter of carbon nanotube growth, a second metal film formed at least on the first metal film in the via hole, and functioning as a catalyst of the carbon nanotube growth, and carbon nanotubes buried in the via hole in which the first metal film and the second metal film are formed. | 09-29-2011 |
20110256672 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof. | 10-20-2011 |
20110309517 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device including a substrate provided with a semiconductor element, and first and second interconnects provided above the substrate, each of the first and second interconnects having a line shape in a plan view, and the first and second interconnects being substantially parallel to each other. The device further includes a first via plug provided above the substrate, electrically connected to a lower surface of the first interconnect on a second interconnect side, and including a first recess part at an upper end of the first via plug under a first region between interconnects, the first region between interconnects being a region between the first interconnect and the second interconnect. The device further includes a via layer insulator provided above the substrate and including the first via plug, and a first trench under the first region between interconnects, the first trench including a region adjacent to the first via plug in a width direction of the first and second interconnects. Furthermore, an air gap is included in the first region between interconnects and in the first trench. | 12-22-2011 |
20120080661 | GRAPHENE INTERCONNECTION AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench. | 04-05-2012 |
20120080662 | GRAPHENE INTERCONNECTION AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a graphene interconnection includes a first insulating film, a first catalyst film, and a first graphene layer. A first insulating film includes an interconnection trench. A first catalyst film is formed on the first insulating film on both side surfaces of the interconnection trench. A first graphene layer is formed on the first catalyst film on the both side surfaces of the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to the both side surfaces. | 04-05-2012 |
20120080796 | DEVICE - According to one embodiment, a device includes an insulating layer with a first trench, a first interconnect layer in the first trench, the first interconnect layer including copper and includes a concave portion, and a first graphene sheet on an inner surface of the concave portion. | 04-05-2012 |
20120187569 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first insulating film formed on a substrate and including a first area and a second area; a groove formed in the first area of the first insulating film; a plurality of first wiring lines formed in the groove and on the first insulating film, and a second insulating film covering a top surface of the first insulating film and top surfaces of the first wiring lines, the plurality of first wiring lines are parallel to a sidewall of the groove and apart from each other with a first predetermined distance, and the first wiring line closest to the sidewall is apart from the sidewall with a second predetermined distance. | 07-26-2012 |
20120228614 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate. | 09-13-2012 |
20130056873 | SEMICONDUCTOR DEVICE - According to an embodiment of the present invention, a device includes a substrate, a base body formed on or above the substrate, and a pair of wirings. The base body has a line shape in a plan view and extends along a length direction. The pair of wirings includes first and second catalyst layers formed on both side surfaces of the base body in the length direction of the base body with sandwiching the base body; and first and second graphene layers formed on both side surfaces of the base body in a manner of contacting the first and second catalyst layers, respectively, and extending along the length direction of the base body, the graphene layers includes a plurality of graphenes laminated perpendicularly with respect to both side surfaces of the base body, respectively. | 03-07-2013 |
20130217226 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer. | 08-22-2013 |
20140061916 | SEMICONDUCTOR DEVICE WITH LOW RESISTANCE WIRING AND MANUFACTURING METHOD FOR THE DEVICE - According to one embodiment, a semiconductor device includes an insulating film, a catalytic layer and a wiring layer. The insulating film has a hole. The catalytic layer is formed at the bottom of the hole, at the peripheral wall of the hole, and on the upper surface of the insulating film outside the hole. A contact is formed of a carbon nanotube provided on the portion of the catalytic layer at the bottom of the hole. The wiring layer is formed of graphene and provided on the catalytic layer outside the hole in contact with the carbon nanotube. The catalytic layer at the bottom of the hole is a perforated film, and the catalytic layer outside the hole is a continuous film. | 03-06-2014 |
20140070425 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires. | 03-13-2014 |
20140084250 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer. | 03-27-2014 |
20140231751 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire. | 08-21-2014 |
20140264718 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof. | 09-18-2014 |
20140284802 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another. | 09-25-2014 |
20150035149 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor substrate provided with a lower interconnect layer formed thereon, and having a device region and a mark formation region, a CNT via structure formed in the device region such that it contacts the lower interconnect layer, a first mark formed in the mark formation region, formed by embedding carbon nanotubes, and formed in the same layer as the CNT via structure, a second mark formed in the mark formation region of the semiconductor substrate, formed with no carbon nanotubes, and formed in the same layer as the CNT via structure and the first mark, and an interconnect layer formed on the CNT via structure and the first and second marks, and electrically connected to the CNT via structure. | 02-05-2015 |
20150056807 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires. | 02-26-2015 |