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Makoto Wada
Makoto Wada, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090085214 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member, a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member. | 04-02-2009 |
| 20090206491 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region. | 08-20-2009 |
| 20090289281 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the same line width and pitch as those of the plurality of bit lines in the memory device region; and an upper-layer contact plug arranged from an upper-layer side so as to be connected to the plurality of shunt lines by extending over two or more shunt lines. | 11-26-2009 |
| 20100181673 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C. | 07-22-2010 |
| 20110006425 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate and containing a wiring trench; a first catalyst layer provided directly or via another member on side and bottom surfaces of the wiring trench; and a first graphene layer provided in the wiring trench so as to be along the side and bottom surface of the wiring trench, the first graphene layer being provided on the first catalyst layer so as to be in contact with the first catalyst layer. | 01-13-2011 |
| 20110101528 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a substrate; a wiring provided above the substrate and including a graphene nanoribbon layer comprising a plurality of laminated graphene nanoribbon sheets; and a wiring connecting member penetrating at least one of the plurality of graphene nanoribbon sheets for connecting the wiring and a conductive member above or below the wiring. | 05-05-2011 |
Makoto Wada, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100213526 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof. | 08-26-2010 |
| 20110057322 | CARBON NANOTUBE INTERCONNECT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a carbon nanotube interconnect includes a first interconnection layer, an interlayer dielectric film, a second interconnection layer, a contact hole, a plurality of carbon nanotubes and a film. The interlayer dielectric film is formed on the first interconnection layer. The second interconnection layer is formed on the interlayer dielectric film. The contact hole is formed in the interlayer dielectric film between the first interconnection layer and the second interconnection layer. The carbon nanotubes are formed in the contact hole. The carbon nanotubes have a first end connected to the first interconnection layer and a second end connected to the second interconnection layer. The film is formed between the interlayer dielectric film and the second interconnection layer. The film has a portion filled between the second ends of the carbon nanotubes. | 03-10-2011 |
Makoto Wada, Fukuoka JP
| Patent application number | Description | Published |
|---|---|---|
| 20100145515 | ROBOT SYSTEM AND CONTROL METHOD - A robot system includes a robot arm driven by a motor, a collision detector that detects a collision between the robot arm and an obstacle, which is provided on the robot arm, and a stopping method selector that controls the robot arm by selecting any one of all stopping methods on the basis of the information obtained by the collision detector, thereby selecting a stopping method in accordance with the status of the collision. | 06-10-2010 |
Makoto Wada, Saitama JP
| Patent application number | Description | Published |
|---|---|---|
| 20090317691 | Ejector for fuel cell system - An ejector for a fuel cell system of the present invention includes a nozzle having a nozzle hole for discharging hydrogen supplied via an inlet port of an ejector body, a diffuser for mixing hydrogen discharged from the nozzle hole and hydrogen off-gas discharged and returned via a circulation passage from a fuel cell, a needle displacing in the axial direction by a driving force of a solenoid, and a bearing member held in a hollow portion of the nozzle, and having a through hole that movably supports the needle in the axial direction. | 12-24-2009 |
Makoto Wada, Kanagawa-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20090191712 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a line portion of the pattern from both longitudinal sides of the line portion until the width of the line portion is reduced to approximately one third, reforming a part of the amorphous silicon layer where the first film is not provided such that reformed part has different etching ratio, and removing the first film and the amorphous silicon layer other than reformed part. | 07-30-2009 |
Makoto Wada, Sendai-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110189849 | SEMICONDUCTOR DEVICE WITH A BARRIER FILM - A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film. | 08-04-2011 |