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| 20100165733 | NAND NONVOLATILE SEMICONDUCTOR MEMORY - A NAND nonvolatile semiconductor memory includes a plurality of series-connected memory cells each includes a charge storage layer and control gate electrode, a plurality of word lines respectively connected to control gate electrodes of the memory cells, a first selection transistor connected between one end of the memory cells and a source line, a second selection transistor connected between the other end of the memory cells and a bit line, and a driver configured to control voltages applied to the word lines. The driver applies a first voltage to a first word line connected to a selected memory cell, and applies a cutoff voltage that cuts off a channel of a memory cell to second word lines of a number not less than three arranged side by side on the source line side with respect to the first word line during a write operation. | 07-01-2010 |
| 20110075485 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device according to one aspect of the present invention includes a plurality of sense amplifier circuit that are configured to carry out a plurality of read cycles on a plurality of bit lines connected to those memory cells that are selected by a selected one of the word lines. During the second and subsequent read cycles, supply of a read current is ceased to those bit lines when it is determined in the preceding read cycle that a current not less than a certain determination current level flows therethrough, and the read current is supplied only to the remaining bit lines. A setup time of the bit lines in the first read cycle is set shorter than a setup time of the bit lines in the second and subsequent read cycles. | 03-31-2011 |
| 20110176366 | SEMICONDUCTOR STORAGE DEVICE AND READING METHOD THEREOF - An embodiment of the invention provides a semiconductor storage device including a NAND string, a SEN node, and a capacitor. The NAND string includes plural series-connected memory cells, and one end of the NAND string is connected to a bit line while the other end is connected to a common source line. The SEN node is configured to be able to be electrically connected to a voltage source and the bit line. In the capacitor, one end is connected to the SEN node while the other end is connected to a CLK node to which a voltage within a predetermined range is applied. A discharge rate of the SEN node is enhanced by decreasing a capacitance during discharge of the SEN node only when a selected memory cell selected from the plural memory cells is an on-cell. | 07-21-2011 |
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| 20090154241 | NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD - A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory. | 06-18-2009 |
| 20090185423 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction. | 07-23-2009 |
| 20100128526 | MULTI-LEVEL NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells which are connected in series between the first and second select gate transistors, a selected word line which is connected to a selected memory cell as a target of a reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which changes a set up term of the selected word line and the non-selected word line based on a value of the selected read potential, wherein the value of the selected read potential is selected from two or more potentials. | 05-27-2010 |
| 20100135078 | NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value. | 06-03-2010 |
| 20100177563 | NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD - A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory. | 07-15-2010 |
| 20100232233 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device in which a negative-threshold cell read operation is performed by biasing a source line and well line to a positive voltage includes a first drive circuit that sets at least unselected word line in a floating state at a negative-threshold cell read time. | 09-16-2010 |
| 20110063911 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction. | 03-17-2011 |
| 20110286268 | NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value. | 11-24-2011 |
| 20110299339 | NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD - A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory. | 12-08-2011 |
| 20110310667 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction. | 12-22-2011 |
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| 20090155580 | Production Methods of Semiconductor Crystal and Semiconductor Substrate - To provide a semiconductor substrate of high quality suitable for fabricating an electronic device or an optical device. The present invention provides a method for producing a semiconductor substrate for an electronic device or an optical device, the method including reacting nitrogen (N) with gallium (Ga), aluminum (Al), or indium (In), which are group III elements, in a flux mixture containing a plurality of metal elements selected from among alkali metals and alkaline earth metals, to thereby grow a group III nitride based compound semiconductor crystal. The group III nitride based compound semiconductor crystal is grown while the flux mixture and the group III element are mixed under stirring. At least a portion of a base substrate on which the group III nitride based compound semiconductor crystal is grown is formed of a flux-soluble material, and the flux-soluble material is dissolved in the flux mixture, at a temperature near the growth temperature of the group III nitride based compound semiconductor crystal, during the course of growth of the semiconductor crystal or after completion of growth of the semiconductor crystal. | 06-18-2009 |
| 20090169444 | Apparatus for Producing Group III Nitride Based Compound Semiconductor - An object of the invention is to prevent, in the flux method, diffusion of substances that constitute the atmosphere of the outer vessel into the reactor. | 07-02-2009 |
| 20090173273 | Method and Apparatus for Producing Group III Nitride Based Compound Semiconductor - In the flux method, a source nitrogen gas is sufficiently heated before feeding to an Na—Ga mixture. | 07-09-2009 |
| 20100093157 | METHOD FOR PRODUCING GROUP III NITRIDE-BASED COMPOUND SEMICONDUCTOR CRYSTAL - A GaN single crystal | 04-15-2010 |
| 20100301358 | Semiconductor Substrate, Electronic Device, Optical Device, and Production Methods Therefor - The present invention provides a method for producing a semiconductor substrate, the method including reacting nitrogen (N) with gallium (Ga), aluminum (Al), or indium (In), which are group III elements, in a flux mixture containing a plurality of metal elements selected from among alkali metals and alkaline earth metals, to thereby grow a group III nitride based compound semiconductor crystal. The group III nitride based compound semiconductor crystal is grown while the flux mixture and the group III element are mixed under stirring. At least a portion of a base substrate on which the group III nitride based compound semiconductor crystal is grown is formed of a flux-soluble material, and the flux-soluble material is dissolved in the flux mixture, at a temperature near the growth temperature of the group III nitride based compound semiconductor crystal, during the course of growth of the semiconductor crystal. | 12-02-2010 |
