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Maiz, US

Jose Maiz, Portland, OR US

Patent application numberDescriptionPublished
20080203388Apparatus and method for detection of edge damages - Embodiments of the invention enable detection of edge damages in semiconductor devices. To this purpose, one or more continuity structures may be provided, where each structure comprises an undulating arrangement disposed between active circuits of the semiconductor device and a perimeter of the metallization layers. The continuity structure(s) forms one or more conductive paths intersecting a plurality of metallization layers in the semiconductor device. A relative change in an electrical characteristic of the continuity structure(s) is monitored to ascertain whether or not an edge damage is present.08-28-2008
20080242012High quality silicon oxynitride transition layer for high-k/metal gate transistors - A method for fabricating a high quality silicon oxynitride layer for a high-k/metal gate transistor comprises depositing a high-k dielectric layer on a substrate, depositing a barrier layer on the high-k dielectric layer, wherein the barrier layer includes at least one of nitrogen or oxygen, depositing a capping layer on the barrier layer, and annealing the substrate at a temperature that causes at least a portion of the nitrogen and/or oxygen in the barrier layer to diffuse to an interface between the high-k dielectric layer and the substrate. The diffused nitrogen or oxygen forms a high-quality silicon oxynitride layer at the interface. The high-k dielectric layer, the barrier layer, and the capping layer may then be etched to form a gate stack for use in a high-k/metal gate transistor. The capping layer may be replaced with a metal gate electrode using a replacement metal gate process.10-02-2008
20090058540Microelectronic Die Having CMOS Ring Oscillator Thereon And Method of Using Same - A microelectronic die including a CMOS ring oscillator thereon, and a method of using the same. The microelectronic die includes: a die substrate; and a plurality of CMOS ring oscillators on the die substrate, the ring oscillators being disposed at regions of the die substrate that are adapted to exhibit differing strain responses to package-induced stress with respect to one another.03-05-2009
20090130293BIOCOMPATIBLE COATINGS FOR MEDICAL DEVICES - Biocompatible coatings for implantable medical devices are disclosed. Embodiments of the invention provide plasma etch processes, surface silanization processes, and protein coating processes. Embodiments of the invention provide tropoelastin coatings and methods of creating tropoelastin coatings for implantable medical devices. Optionally, the biocompatible coating can be a drug eluting coating.05-21-2009
20090169714BIOCOMPATIBLE COATINGS FOR MEDICAL DEVICES - Biocompatible coatings for implantable medical devices are disclosed. Embodiments of the invention provide methods for coating an object with a biocompatible coating wherein the device is suspended using a flowing gas during the coating process. Embodiments of the invention provide tropoelastin coatings and methods of creating tropoelastin coatings for implantable medical devices. Optionally, the biocompatible coating can be a drug eluting coating.07-02-2009

Patent applications by Jose Maiz, Portland, OR US

Jose A. Maiz, Portland, OR US

Patent application numberDescriptionPublished
20100070809REPAIR BITS FOR A LOW VOLTAGE CACHE - A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.03-18-2010
20100219529METHOD AND APPARATUS FOR FORMING METAL-METAL OXIDE ETCH STOP/BARRIER FOR INTEGRATED CIRCUIT INTERCONNECTS - Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.09-02-2010

Patent applications by Jose A. Maiz, Portland, OR US

Julia Louise Maiz, Chino Hills, CA US

Patent application numberDescriptionPublished
20090011395SYSTEM AND METHODS FOR MATCHING REQUIREMENTS AND STANDARDS IN EMPLOYMENT AND EDUCATION-RELATED ENVIRONMENTS - Systems and methods of developing online courses suited to the needs of employers are provided. A course creation module allows employers or other interested parties specify desired attributes for prospective employees using a course creation module. Online courses are developed based on these specified needs.01-08-2009