| Patent application number | Description | Published |
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| 20080261413 | PRETREATMENT PROCESSES WITHIN A BATCH ALD REACTOR - Embodiments of the invention provide methods for forming a hafnium material on a substrate within a processing chamber. In one embodiment, a method is provided which includes exposing the substrate within the processing chamber to a first oxidizing gas during a pretreatment process, exposing the substrate sequentially to a second oxidizing gas and a deposition gas during an atomic layer deposition (ALD) cycle, wherein the second oxidizing gas contains water and the deposition gas contains a hafnium amino compound, and repeating the ALD cycle to form a hafnium-containing layer having a thickness within a range from about 5 Å to about 300 Å. In one example, the first oxidizing gas contains an O | 10-23-2008 |
| 20090016406 | NOVEL METHOD FOR MONITORING AND CALIBRATING TEMPERATURE IN SEMICONDUCTOR PROCESSING CHAMBERS - The present invention provides a non-destructive method for monitoring and calibrating chamber temperature. One embodiment of the present invention provides a method for measuring temperature comprising forming a target film on a test substrate at a first temperature, wherein the target film has one or more properties responsive to thermal exposure, exposing the target film to an environment at a second temperature in a range higher than the first temperature, measuring the one or more properties of the target film after exposing the target film to the environment at the second temperature, and determining the second temperature according to the measured one or more properties. | 01-15-2009 |
| 20090017637 | METHOD AND APPARATUS FOR BATCH PROCESSING IN A VERTICAL REACTOR - The present invention generally provides an apparatus and method for the processing a plurality of substrates in a batch processing chamber. One embodiment of the present invention provides a method for processing a plurality of substrates comprising positioning the plurality of substrates in an inner volume of a batch processing chamber, wherein the plurality of substrates are arranged in a substantially parallel manner, and at least a portion of the plurality of substrates are positioned with a device side facing downward, and flowing one or more processing gases cross the plurality of substrates. | 01-15-2009 |
| 20090078198 | CHAMBER COMPONENTS WITH INCREASED PYROMETRY VISIBILITY - The present invention generally provides method and apparatus for non-contact temperature measurement in a semiconductor processing chamber. Particularly, the present invention provides methods and apparatus for non-contact temperature measurement for temperature below 500° C. One embodiment of the present invention provides an apparatus for processing semiconductor substrates. The apparatus comprises a target component comprises a material with higher emissivity than the one or more substrates. | 03-26-2009 |
| 20090242957 | ATOMIC LAYER DEPOSITION PROCESSES FOR NON-VOLATILE MEMORY DEVICES - Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer. | 10-01-2009 |
| 20090258462 | METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS - The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells. | 10-15-2009 |
| 20090261343 | HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse. | 10-22-2009 |
| 20100102376 | Atomic Layer Deposition Processes for Non-Volatile Memory Devices - Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate. | 04-29-2010 |
| 20100227061 | LOW TEMPERATURE ALD Si02 - The present invention generally comprises a silicon dioxide atomic layer deposition method. By providing pyridine as a catalyst, water may be utilized as the oxidization source while depositing at a low temperature. Prior to exposing the substrate to the water, the substrate may be exposed to a pyridine soak process. Additionally, the water may be co-flowed to the chamber with the pyridine through separate conduits to reduce interaction prior to entering the chamber. Alternatively, the pyridine may be co-flowed with a silicon precursor that does not react with pyridine. | 09-09-2010 |
| 20110021019 | METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS - The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells. | 01-27-2011 |
