Patent application number | Description | Published |
20080261413 | PRETREATMENT PROCESSES WITHIN A BATCH ALD REACTOR - Embodiments of the invention provide methods for forming a hafnium material on a substrate within a processing chamber. In one embodiment, a method is provided which includes exposing the substrate within the processing chamber to a first oxidizing gas during a pretreatment process, exposing the substrate sequentially to a second oxidizing gas and a deposition gas during an atomic layer deposition (ALD) cycle, wherein the second oxidizing gas contains water and the deposition gas contains a hafnium amino compound, and repeating the ALD cycle to form a hafnium-containing layer having a thickness within a range from about 5 Å to about 300 Å. In one example, the first oxidizing gas contains an O | 10-23-2008 |
20090016406 | NOVEL METHOD FOR MONITORING AND CALIBRATING TEMPERATURE IN SEMICONDUCTOR PROCESSING CHAMBERS - The present invention provides a non-destructive method for monitoring and calibrating chamber temperature. One embodiment of the present invention provides a method for measuring temperature comprising forming a target film on a test substrate at a first temperature, wherein the target film has one or more properties responsive to thermal exposure, exposing the target film to an environment at a second temperature in a range higher than the first temperature, measuring the one or more properties of the target film after exposing the target film to the environment at the second temperature, and determining the second temperature according to the measured one or more properties. | 01-15-2009 |
20090017637 | METHOD AND APPARATUS FOR BATCH PROCESSING IN A VERTICAL REACTOR - The present invention generally provides an apparatus and method for the processing a plurality of substrates in a batch processing chamber. One embodiment of the present invention provides a method for processing a plurality of substrates comprising positioning the plurality of substrates in an inner volume of a batch processing chamber, wherein the plurality of substrates are arranged in a substantially parallel manner, and at least a portion of the plurality of substrates are positioned with a device side facing downward, and flowing one or more processing gases cross the plurality of substrates. | 01-15-2009 |
20090078198 | CHAMBER COMPONENTS WITH INCREASED PYROMETRY VISIBILITY - The present invention generally provides method and apparatus for non-contact temperature measurement in a semiconductor processing chamber. Particularly, the present invention provides methods and apparatus for non-contact temperature measurement for temperature below 500° C. One embodiment of the present invention provides an apparatus for processing semiconductor substrates. The apparatus comprises a target component comprises a material with higher emissivity than the one or more substrates. | 03-26-2009 |
20090242957 | ATOMIC LAYER DEPOSITION PROCESSES FOR NON-VOLATILE MEMORY DEVICES - Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer. | 10-01-2009 |
20090258462 | METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS - The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells. | 10-15-2009 |
20090261343 | HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse. | 10-22-2009 |
20100102376 | Atomic Layer Deposition Processes for Non-Volatile Memory Devices - Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate. | 04-29-2010 |
20100227061 | LOW TEMPERATURE ALD Si02 - The present invention generally comprises a silicon dioxide atomic layer deposition method. By providing pyridine as a catalyst, water may be utilized as the oxidization source while depositing at a low temperature. Prior to exposing the substrate to the water, the substrate may be exposed to a pyridine soak process. Additionally, the water may be co-flowed to the chamber with the pyridine through separate conduits to reduce interaction prior to entering the chamber. Alternatively, the pyridine may be co-flowed with a silicon precursor that does not react with pyridine. | 09-09-2010 |
20110021019 | METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS - The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells. | 01-27-2011 |
20110263115 | NMOS METAL GATE MATERIALS, MANUFACTURING METHODS, AND EQUIPMENT USING CVD AND ALD PROCESSES WITH METAL BASED PRECURSORS - Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for processing a substrate is provided which includes depositing a dielectric material having a dielectric constant greater than 10, forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MX | 10-27-2011 |
20110263137 | PRETREATMENT PROCESSES WITHIN A BATCH ALD REACTOR - Embodiments of the invention provide methods for forming dielectric materials on a substrate. In one embodiment, a method includes exposing a substrate surface to a first oxidizing gas during a pretreatment process, wherein the first oxidizing gas contains a mixture of ozone and oxygen having an ozone concentration within a range from about 1 atomic percent to about 50 atomic percent and forming a hafnium-containing material on the substrate surface by exposing the substrate surface sequentially to a deposition gas and a second oxidizing gas during an atomic layer deposition (ALD) process, wherein the deposition gas contains a hafnium precursor, the second oxidizing gas contains water, and the hafnium-containing material has a thickness within a range from about 5 Å to about 300 Å. In one example, the hafnium-containing material contains hafnium oxide having the chemical formula of HfO | 10-27-2011 |
20110287615 | HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse. | 11-24-2011 |
20120108079 | Atomic Layer Deposition Film With Tunable Refractive Index And Absorption Coefficient And Methods Of Making - Atomic layer deposition methods of forming one or more of a mixed silicon oxide/silicon nitride film or a mixed silicon oxide/silicon film are described in which the substrate is exposed sequentially to a first reactant gas comprising a silicon species and a second reactant gas comprising an oxygen species to form at least a partial layer of silicon oxide on the substrate during a first atomic layer deposition process. The substrate is then exposed sequentially to a third reactant gas comprising a silicon species and a fourth reactant gas comprising a species sufficient to form at least a partial layer of one or more of silicon nitride or silicon on the substrate during a second atomic layer deposition process. The process can be repeated multiple times to deposit one or more of a mixed silicon oxide/silicon nitride film and a mixed silicon oxide/silicon film. | 05-03-2012 |
20120192792 | PLASMA, UV AND ION/NEUTRAL ASSISTED ALD OR CVD IN A BATCH TOOL - CVD and ALD methods of using a batch processing chamber to process substrates are described. A batch processing chamber includes a chamber housing, a substrate boat for containing a batch of substrates in a process region, and an excitation assembly for exciting species of a processing gas. The excitation assembly is positioned within the chamber housing and may include plasma, UV, or ion assistance. | 08-02-2012 |
20120202357 | In Situ Vapor Phase Surface Activation Of SiO2 - Methods for preparing a substrate for a subsequent film formation process are described. Methods for preparing a substrate for a subsequent film formation process, without immersion in an aqueous solution, are also described. A process is described that includes disposing a substrate into a process chamber, the substrate having a thermal oxide surface with substantially no reactive surface terminations. The thermal oxide surface is exposed to a partial pressure of water above the saturated vapor pressure at a temperature of the substrate to convert the dense thermal oxide with substantially no reactive surface terminations to a surface with hydroxyl surface terminations. This can occur in the presence of a Lewis base such as ammonia. | 08-09-2012 |
20120220116 | Dry Chemical Cleaning For Semiconductor Processing - A deposition process including a dry etch process, followed by a deposition process of a high-k dielectric is disclosed. The dry etch process involves placing a substrate to be cleaned into a processing chamber to remove surface oxides. A gas mixture is energized to form a plasma of reactive gas which reacts with an oxide on the substrate, forming a thin film. The substrate is heated to vaporize the thin film and expose a substrate surface. The substrate surface is substantially free of oxides. Deposition is then used to form a layer on the substrate surface. | 08-30-2012 |
20120289052 | Methods for Manufacturing High Dielectric Constant Films - Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface. | 11-15-2012 |
20120289063 | Methods For Manufacturing High Dielectric Constant Films - Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface. | 11-15-2012 |
20120322250 | N-Metal Film Deposition With Initiation Layer - Provided are methods of depositing N-Metals onto a substrate. Some methods comprise providing an initiation layer of TaM or TiM layer on a substrate, wherein M is selected from aluminum, carbon, noble metals, gallium, silicon, germanium and combinations thereof; and exposing the substrate having the TaM or TiM layer to a treatment process comprising soaking the surface of the substrate with a reducing agent to provided a treated initiation layer. | 12-20-2012 |
20120322262 | N-Metal Film Deposition With Initiation Layer - Provided are methods of depositing N-Metals onto a substrate. Methods include first depositing an initiation layer. The initiation layer may comprise or consist of cobalt, tantalum, nickel, titanium or TaAlC. These initiation layers can be used to deposit TaC | 12-20-2012 |
20130122697 | Doping aluminum in tantalum silicide - Provided are methods of providing aluminum-doped TaSi | 05-16-2013 |
20130164921 | HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided. | 06-27-2013 |
20130295759 | Methods For Manufacturing Metal Gates - Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first. | 11-07-2013 |
20140023794 | Method And Apparatus For Low Temperature ALD Deposition - Provided are methods and apparatus for low temperature atomic layer deposition of a densified film. A low temperature film is formed and densified by exposure to one or more of a plasma or radical species. The resulting densified film has superior properties to low temperature films formed without densification. | 01-23-2014 |
20140120712 | NMOS METAL GATE MATERIALS, MANUFACTURING METHODS, AND EQUIPMENT USING CVD AND ALD PROCESSES WITH METAL BASED PRECURSORS - Embodiments provide methods for depositing metal-containing materials. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. A method for processing a substrate is provided which includes depositing a dielectric material forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MX | 05-01-2014 |