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Mahmud, US
Adnan Azfar Mahmud, Kirkland, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20080313149 | Analyzing software usage with instrumentation data - Described is a technology by which software instrumentation data collected from user program sessions are analyzed to output an analysis report or the like via example methods and an architecture configured for efficient operation. A client component queries a service for analysis related information. To process the query, the service works with a data manager, and via a high dimensional analysis component may use information processed from the software instrumentation data, such as in the form of one or more inverted indexes and/or raw value files. The service may include a usage analysis component, a feature recognition component that locates features from command sequences, a user recognition component and/or a program reliability component. One or more counterpart components at the client may generate analysis reports or the like based on the query results. The client also may maintain user libraries and feature libraries to facilitate analyses. | 12-18-2008 |
| 20080313184 | Multidimensional analysis tool for high dimensional data - Described is a technology by which high dimensional data may be efficiently analyzed, including by filtering, grouping, aggregating and/or sorting operations to provide an analysis result. For efficiency in the analysis, an inverted index may be built (e.g., as part of filtering), and/or a hash structure (e.g., as part of grouping). Analysis parameters specify dimensions, on which union and/or intersection operations are performed to provide a final dataset. The analysis tool provides a user interface for inputting analysis parameters and outputting information corresponding to an analysis result. The analysis tool may sort the information corresponding to the analysis result, e.g., to output the topmost or bottommost results. | 12-18-2008 |
| 20080313507 | Software reliability analysis using alerts, asserts and user interface controls - Described is a technology by which software instrumentation data collected during software program usage sessions is analyzed to identify potential problems with software program usage, such as based on frequency of problem occurrence during the usage sessions. Reliability metrics may be calculated from the information. Failure data additionally collected during the usage sessions may be accessed to derive details that correspond to the potential problems. In one example, the information may be analyzed to determine which alerts and/or asserts occurred most often, and/or to determine a relationship between user interface control operations (e.g., clicks and usage of commands) and alerts or asserts. | 12-18-2008 |
| 20080313633 | Software feature usage analysis and reporting - Described is a technology for analyzing usage of a software program's features. Software instrumentation data is during actual user program usage sessions. The collected data is then processed to determine various feature usage counts and other information, cross-feature usage (e.g., among users who use a feature, how many use another feature or program), and characteristics of feature users, e.g., how long, how much, how often and how extensive feature users use a program. Session analysis may be performed to provide information about the number of sessions in which a set of features occur. Feature usage trends over time may also be determined via analysis. A user interface is described for facilitating selection of one or more features to analyze, for facilitating selection of a group of users, and/or for outputting results corresponding to the analysis. | 12-18-2008 |
Arif Mahmud, Chandler, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20080224754 | HIGH-SPEED SERIAL LINK RECEIVER WITH CENTRALLY CONTROLLED OFFSET CANCELLATION AND METHOD - A high-speed serial link receiver includes variable offset comparators with centrally controlled offset cancellation. The receiver includes a comparator stage to receive a high-speed differential input signal. Comparator elements of the comparator stage have first and second current sources to provide current to corresponding differential amplifier half-circuits. An offset cancellation controller provides an offset cancellation signal for setting current provided by one of the current sources to at least partially offset an output offset between the differential amplifier half-circuits. A receiver system may be comprised of a plurality of receiver units for receiving a corresponding plurality of channels over high-speed serial links. A state machine may sequentially determine an offset cancellation code for the comparator elements of the receiver units. | 09-18-2008 |
Jalal U. Mahmud, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110271255 | AUTOMATIC IDENTIFICATION OF SUBROUTINES FROM TEST SCRIPTS - A method, system, and program product for automatic identification of subroutines from test scripts is disclosed. An instruction class may be coded as a subroutine vector in a vector space model. A test script action may be coded as a test script vector in a vector space model. The test script vector may be compared to the subroutine vector. The test script vector may be identified and labeled. The test script vector may be labeled as a new test script action if the result of comparing is below a threshold value. An identifier may be associated with a new test script action. | 11-03-2011 |
Jalal Uddin Mahmud, Centereach, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090100352 | METHOD AND APPARATUS FOR BRIDGING REAL-WORLD WEB APPLICATIONS AND 3D VIRTUAL WORLDS - A computer implemented method, data processing system, and computer program product for automating information sharing and propagation of control commands and events between software objects created in Web applications and 3D virtual world objects created in virtual world applications. A relationship is created to link a Web object with one or more virtual world objects, or to link a virtual world object with one or more Web objects. A Web application may retrieve the meta-data of one or more virtual world objects or send commands or events to manipulate one or more virtual world objects to which a Web object within the Web application is linked. A virtual world system may retrieve the meta-data of one or more Web objects or send commands or events to manipulate one or more Web objects to which a virtual world object within the virtual world system is linked. | 04-16-2009 |
| 20090216546 | Rating Virtual World Merchandise by Avatar Visits - A computer implemented method and apparatus to generate popularity ratings for virtual world artifacts based on how often and in what manner avatars access the artifacts. The popularity ratings for virtual world artifacts may be used to determine what virtual world artifacts are selected to have a prominent presence in a virtual world. When an event caused by an avatar accessing a virtual world artifact in a virtual world is detected, the illustrative embodiments receive information about the event, such as the event type, the avatar identifier (ID), and the time the event occurred. The illustrative embodiments generate a rating score for the virtual world artifact based on the information received about the event. The illustrative embodiments update a rendering of the virtual world artifact in the virtual world based on the rating score. | 08-27-2009 |
Ken Mahmud, Sudbury, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20090317913 | DETECTION OF PEROXIDE RADICALS AND REACTION INITIATORS - Sensors including a functional component, methods for making such sensors and methods for using sensors including a functional component for the detection of free radical forming compounds including peroxides and devices incorporating such sensors are provided herein. | 12-24-2009 |
Mainuddin Mahmud, Oak Ridge, NJ US
| Patent application number | Description | Published |
|---|---|---|
| 20110111018 | COATED TABLET FORMULATIONS AND USES THEREOF - The present invention provides coated tablet formulations comprising neratinib maleate, and improved methods for making such coated tablets. | 05-12-2011 |
Naila Mahmud, Great Neck, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100017250 | SYSTEMS, APPARATUS, AND METHODS FOR FACILITATING PRODUCT DEVELOPMENT - Systems, apparatus, and methods are provided to facilitate product development by linking stages of product development with the allocation of resources and support for the product. Products are developed based on a structured framework having distinct stages in which each stage builds upon information of previous stages. At the end of each stage, a review is conducted to determine whether the product is suitable for further development. Upon each review, an integrated set of tools is used to identify and link the product with resources and support needed for the product. In addition, the tools assist in automatically identifying the resources and support needed for the product as it progresses through each stage. | 01-21-2010 |
Sayeed Mahmud, Carrollton, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110225030 | INTEGRATED QUALIFICATION AND MONITORING FOR CUSTOMER PROMOTIONS - A device receives, from a user device, a request for qualified offers for a particular customer, and retrieves, based on the request, profile information associated with the particular customer. The device generates a call to a backend database based on the profile information, and receives, from the backend database, offer qualification indicators based on the call. The device determines qualified offers based on the offer qualification indicators, and provides the qualified offers to the user device for display. | 09-15-2011 |
Taifo Mahmud, Corvallis, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20100151528 | METHODS OF PRODUCING VALIDAMYCIN A ANALOGS AND USES THEREOF - This disclosure relates to validamycin A biosynthesis and in particular, to methods of producing validamycin A analogs and uses thereof. In a particular example, a method for making a validamycin A analog includes transforming a host cell with one or more recombinant DNA vectors to produce a valN-inactivated mutant; and culturing the valN-inactivated mutant in a culture medium to produce a validamycin A analog, such as 1,1′-bis-valienamine and validienamycin, and their conversion to valienamine. The present disclosure further relates to compositions including such compounds as well as methods of using the compositions, such as for antifungal agents. | 06-17-2010 |
| 20100210837 | PACTAMYCIN BIOSYNTHETIC GENE CLUSTER - This disclosure describes the molecular cloning of a pactamycin biosynthetic gene cluster from | 08-19-2010 |
Tuhin Mahmud, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080295051 | SLEW CONSTRAINED MINIMUM COST BUFFERING - A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution. | 11-27-2008 |
| 20090013299 | BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS - Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering. | 01-08-2009 |
| 20090064080 | BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS - Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering. | 03-05-2009 |
| 20090259980 | Method and System for Concurrent Buffering and Layer Assignment in Integrated Circuit Layout - A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or “wires” are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the “slack” gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources. | 10-15-2009 |