Patent application number | Description | Published |
20100279467 | METHODOLOGY FOR PROCESSING A PANEL DURING SEMICONDUCTOR DEVICE FABRICATION | 11-04-2010 |
20110143476 | ELECTRICAL COUPLING OF WAFER STRUCTURES - A method for electrically coupling a first wafer with a second wafer is provided. The method includes bonding the first wafer with the second wafer using a bonding material. The method further includes forming an opening in the first wafer in a scribe area of the second wafer to expose a surface of a conductive structure of the second wafer. The method further includes forming a conductive layer overlying the first wafer and the opening in the first wafer such that the conductive layer forms an electrical contact with the conductive structure of the second wafer thereby electrically coupling the first wafer with the second wafer. | 06-16-2011 |
20130207255 | SEMICONDUCTOR DEVICE PACKAGE HAVING BACKSIDE CONTACT AND METHOD FOR MANUFACTURING - A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive. | 08-15-2013 |
20140001616 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURE | 01-02-2014 |
20140134799 | WETTABLE LEAD ENDS ON A FLAT-PACK NO-LEAD MICROELECTRONIC PACKAGE - Methods of manufacturing a flat-pack no-lead microelectronic package ( | 05-15-2014 |
20140145325 | ELECTRONIC DEVICES WITH EMBEDDED DIE INTERCONNECT STRUCTURES, AND METHODS OF MANUFACTURE THEREOF - An embodiment of an electronic device includes an IC die with a top surface and a bond pad exposed at the top surface. A stud bump (or stack of stud bumps) is connected to the bond pad, and the stud bump and die are encapsulated with encapsulant. A trench is formed from a top surface of the encapsulant to the stud bump, resulting in the formation of a trench-oriented surface of the stud bump, which is exposed at the bottom of the trench. An end of an interconnect is connected to the trench-oriented surface of the stud bump. The interconnect extends above the encapsulant top surface, and may be coupled to another IC die of the same electronic device, another IC die that is distinct from the device, or another conductive feature of the device or a larger electronic system in which the device is incorporated. | 05-29-2014 |
20140167247 | SEMICONDUCTOR DEVICE PACKAGE HAVING BACKSIDE CONTACT AND METHOD FOR MANUFACTURING - A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive. | 06-19-2014 |
20140338956 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURE - A structure and method to improve saw singulation quality and wettability of integrated circuit packages ( | 11-20-2014 |
20140353772 | MICROELECTRONIC PACKAGES INCLUDING PATTERNED DIE ATTACH MATERIAL AND METHODS FOR THE FABRICATION THEREOF - Embodiments of microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the fabrication method includes printing a patterned die attach material onto the backside of a wafer including an array of non-singulated microelectronic die each having an interior keep-out area, such as a central keep-out area. The die attach material, such as a B-stage epoxy, is printed onto the wafer in a predetermined pattern such that the die attach material does not encroaching into the interior keep-out areas. The wafer is singulated to produce singulated microelectronic die each including a layer of die attach material. The singulated microelectronic die are then placed onto leadframes or other package substrates with the die attach material contacting the package substrates. The layer of die attach material is then fully cured to adhere an outer peripheral portion of the singulated microelectronic die to its package substrate. | 12-04-2014 |
20150115454 | MICROELECTRONIC PACKAGES HAVING LAYERED INTERCONNECT STRUCTURES AND METHODS FOR THE MANUFACTURE THEREOF - Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure. | 04-30-2015 |
20150137381 | OPTICALLY-MASKED MICROELECTRONIC PACKAGES AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers. | 05-21-2015 |
20150217998 | SHIELDING MEMS STRUCTURES DURING WAFER DICING - A MEMS wafer ( | 08-06-2015 |
20150228560 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURE - A structure to improve saw singulation quality and wettability of integrated circuit packages ( | 08-13-2015 |
20150232332 | METHOD FOR SHIELDING MEMS STRUCTURES DURING FRONT SIDE WAFER DICING - A method includes applying a compressive force against MEMS structures at a front side of a MEMS wafer using a protective material covering at least a portion of the front side of the MEMS wafer. The method further includes concurrently dicing through the protective material and the MEMS wafer from the front side to produce a plurality of MEMS dies, each of which includes at least one of the MEMS structures. The protective material is secured over the front side of the MEMS wafer to apply pressure to the protective material, and thereby impart the compressive force against the MEMS structures to largely limit movement of the MEMS structures during dicing. A tack-free surface of the protective material enables its removal following dicing. | 08-20-2015 |
20150270233 | WAFER LEVEL PACKAGES AND METHODS FOR PRODUCING WAFER LEVEL PACKAGES HAVING DELAMINATION-RESISTANT REDISTRIBUTION LAYERS - Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer. | 09-24-2015 |
20150333028 | WAFER LEVEL PACAKGES HAVING NON-WETTABLE SOLDER COLLARS AND METHODS FOR THE FABRICATION THEREOF - Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings. | 11-19-2015 |
20160064341 | MICROELECTRONIC PACKAGES HAVING TEXTURIZED SOLDER PADS AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions. | 03-03-2016 |
Patent application number | Description | Published |
20110307275 | INTEGRATED METHOD AND SYSTEM FOR CREATING, GENERATING (PRINTING), MANAGING, AND TRACKING AUTHORIZATIONS TO RELEASE INFORMATION TO THIRD PARTIES - A method and system for preparing release of information documents is disclosed. The method includes receiving first information identifying a particular legal matter, receiving second information identifying one or more clients associated with the particular legal matter, receiving third information identifying a plurality of sources of medical information requiring a release of information document, and receiving fourth information identifying at least one recipient to which said medical information is to be provided. The method further includes batch processing, via a processor, the received first, second, third and fourth information, and generating, via the processor, at least a release of information document for each of the plurality of sources. | 12-15-2011 |
20140095407 | INTEGRATED METHOD AND SYSTEM FOR REAL TIME BI-DIRECTIONAL COMMUNICATIONS OF ISSUES, CONCERNS, PROBLEMS, CRITICISMS, COMPLAINTS, FEEDBACK, OR COMPLIMENTS AND MANAGING, TRACKING, RESPONDING AND AUTOMATING RESPONSES TO SAME - A method and system whereby an Individual can communicate with an organization, business, service provider, healthcare provider or other enterprise (“Enterprise”) wherein the Enterprise can in turn manage, track, respond to, and automate responses to the communication of the Individual. This bi-directional communication can be conducted using a mobile device such as a smart phone or tablet or through a computer connected to the Internet. The Enterprise has a dashboard-like software application to manage, track, measure, and respond to the Individual that has initiated the communication. The Individual may choose to communicate anonymously with the communication stream moving through a third-party server which can serve as an anonymous proxy for the Individual. | 04-03-2014 |
20160004823 | INTEGRATED METHOD AND SYSTEM FOR CREATING, GENERATING (PRINTING), MANAGING, AND TRACKING AUTHORIZATIONS TO RELEASE INFORMATION TO THIRD PARTIES - A method and system for preparing release of information documents is disclosed. The method includes receiving first information identifying a particular legal matter, receiving second information identifying one or more clients associated with the particular legal matter, receiving third information identifying a plurality of sources of medical information requiring a release of information document, and receiving fourth information identifying at least one recipient to which said medical information is to be provided. The method further includes batch processing, via a processor, the received first, second, third and fourth information, and generating, via the processor, at least a release of information document for each of the plurality of sources. | 01-07-2016 |
Patent application number | Description | Published |
20100292466 | Efficient Synthesis Of Galanthamine - The present invention relates to methods for the synthesis of galanthamine, morphine, intermediates, salts and derivatives thereof. In preferred embodiments, the invention relates to methods for improving the efficiency and overall yield of said morphine, morphine related derivatives and intermediates thereof. In further embodiments, the invention relates to methods for improving the efficiency and overall yield of galanthamine and intermediates thereof. | 11-18-2010 |
20100292475 | Efficient Synthesis Of Morphine And Codeine - The present invention relates to methods for the synthesis of morphine, intermediates, salts and derivatives thereof. In preferred embodiments, the invention relates to methods for improving the efficiency and overall yield of said morphine, morphine related derivatives and intermediates thereof. In further embodiments, the invention relates to methods for improving the efficiency and overall yield of galanthamine and intermediates thereof. | 11-18-2010 |
20100292489 | Cross-conjugated 2,5-cyclohexadienone and related synthesis methods - The present invention relates to methods for the synthesis of galanthamine, morphine, intermediates, salts and derivatives thereof. In preferred embodiments, the invention relates to methods for improving the efficiency and overall yield of said morphine, morphine related derivatives and intermediates thereof. In further embodiments, the invention relates to methods for improving the efficiency and overall yield of galanthamine and intermediates thereof. | 11-18-2010 |