Patent application number | Description | Published |
20090265401 | Method, System and Computer Program Product for Shrinking a File System - Computer implemented method, system and computer program product for shrinking a file system in a data processing system. A computer implemented method for shrinking a file system in a data processing system includes designating an amount by which a file system comprised of a plurality of contiguous blocks is to be shrunk, and removing at least one contiguous intermediate block of the plurality of contiguous blocks from the file system to shrink the file system by the designated amount. | 10-22-2009 |
20100037048 | INPUT/OUTPUT CONTROL AND EFFICIENCY IN AN ENCRYPTED FILE SYSTEM - An approach for improving input/output control and efficiency in an encrypted file system (EFS) is provided. In this approach, a software application writes data to a first buffer and then requests that an encrypted file system save the data onto a nonvolatile storage device. The encrypted file system encrypts the data and stores the encrypted data in a second buffer and then writes the encrypted data from the second buffer to the nonvolatile storage area. Meanwhile, the software application is able to resume writing additional data to the buffer after the data has been copied to the second buffer even if the data has not yet been written to the nonvolatile storage area | 02-11-2010 |
20120066189 | CONTROLLING AND RECOVERING LONG-LIVED TRANSACTIONS - Some embodiments of the inventive subject matter are directed to performing sub-transactions of a long-lived transaction (LLT) in a sequence (e.g., according to an LLT flow) and writing a log entry at the performance of each of the sub-transactions that specifies results of the sub-transaction. Some embodiments do not require generating any compensating transactions during performance of the sub-transactions. Some embodiments are further directed to detecting that an interruption occurs to the LLT and repeating, or initiating re-performance of the LLT from the beginning of the sequence following the flow of the LLT from its beginning. During the re-performance of the LLT, some embodiments are further directed to checking the log entry at each sub-transaction to determine whether the sub-transaction was performed successfully before the interruption. If the log indicates that the long-lived transaction completed successfully, some embodiments are further directed to skipping performance of the sub-transaction until reaching a sub-transaction that does not have a valid log entry, then returning an error and recovering the LLT using instructions for compensating transactions that are already written into the LLT flow. | 03-15-2012 |
20130031068 | CONTROLLING AND RECOVERING LONG-LIVED TRANSACTIONS - Some embodiments of the inventive subject matter are directed to performing sub-transactions from a long-lived transaction using an identifier, wherein the sub-transactions are required to be completed in a sequence for the long-lived transaction. In some embodiments, the method is further directed to determining that the sub-transactions require a write of a data value to a database, writing in a log, using the identifier, an entry that indicates the data value, detecting an interruption in performing of the write of the data value to the database, and initiating re-performance of the sub-transactions in order of the sequence. Some embodiments are further directed to, during re-performance of the sub-transactions, detecting the data value in the entry of the log using the identifier, and using the data value indicated in the entry of the log to write the data value to the database. | 01-31-2013 |
20150178219 | Application Startup Page Fault Management in a Hardware Multithreading Environment - A method, system and computer-usable medium are disclosed for startup page fault management improves application startup performance by assigning startup tasks to a hardware thread 0 across plural processing cores in a simultaneous multithreading environment to provide more rapid processing of processor bound page faults. I/O bound page faults are flagged to associated with predetermined cache locations to improve data and text first reference page-in I/O response. | 06-25-2015 |
Patent application number | Description | Published |
20090154220 | PLATELINE DRIVER FOR A FERROELECTRIC MEMORY - One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory cells that are arranged in a number of plateline groups. The memory device also includes a plateline driver configured to boost a plateline voltage above a supply voltage within the plateline driver, and provide the boosted plateline voltage along platelines associated with the plateline driver. Other methods and systems are also disclosed. | 06-18-2009 |
20090168489 | FERROELECTRIC MEMORY DEVICES WITH PARTITIONED PLATELINES - One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to the memory cells of the row and also includes at least two platelines associated with the row. At least one of the at least two platelines is associated with adjacent columns of ferroelectric memory cells within the row. The row of ferroelectric memory cells includes another word line which is not associated with the at least two platelines. Other methods and systems are also disclosed. | 07-02-2009 |
20090168490 | FERROELECTRIC MEMORY CELL WITH ACCESS TRANSMISSION GATE - One embodiment relates to an integrated circuit that includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric capacitor having a first plate and a second plate. The first plate is associated with a storage node of the ferroelectric memory cell, and the second plate associated with a plateline. The ferroelectric memory cell also includes a complementary transmission gate configured to selectively couple the storage node to a bitline as a function of a wordline voltage and a complementary wordline voltage. Bias limiting circuitry selectively alters voltage on the storage node as a function of the wordline voltage or the complementary wordline voltage. Other methods, devices, and systems are also disclosed. | 07-02-2009 |
20100211853 | High Reliability and Low Power Redundancy for Memory - An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request. | 08-19-2010 |
20100226162 | Memory Array Power Domain Partitioning - An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory. | 09-09-2010 |
20110035644 | Data Path Read/Write Sequencing for Reduced Power Consumption - A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The memory stores data in the form of multi-byte data words with error correction coding (ECC). In a page mode read/write operation, data states stored in memory cells of the selected row are sensed by sense amplifiers arranged in first and second banks, which are associated with first and second groups of columns. The first bank of sense amplifiers, associated with the first group of columns and containing the ECC value, are coupled to to the internal bus, followed by coupling the second bank of sense amplifiers associated with the second group of columns to the internal bus. The internal bus is then placed in tri-state, following which the internal data bus is driven with data to be written into the second group of columns in that same row, that data latched into the second bank of sense amplifiers. The internal bus is then driven with the data to be written to the first group of columns in the row, and latched into the first bank of sense amplifiers. To the extent that the data in the second group of columns does not change from the read to write operations, power consumption otherwise necessary for switching the internal bus is avoided. | 02-10-2011 |
20110231736 | Low-Power Redundancy for Non-Volatile Memory - A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array. | 09-22-2011 |
20130051109 | Method of reading a ferroelectric memory cell - A method of reading a memory cell is disclosed. The method includes the step of connecting ( | 02-28-2013 |
20130093245 | METHOD TO MAINTAIN POWER SUPPLY VOLTAGE DURING BROWNOUT - A method of maintaining a power supply voltage during a brownout is disclosed. The method includes the step of storing a charge in a charge reservoir ( | 04-18-2013 |