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Luthra
Ajay K. Luthra, Middlesex GB
| Patent application number | Description | Published |
|---|---|---|
| 20110274821 | HEPARIN COATINGS - The invention includes a medical hydrogel made from polymerized polysaccharide macromers. The macromers are preferably polysaccharides decorated with polymerizable groups, for example, methacrylates. The macromers may also be made into polymers of at least two macromers polymerized together. These polymers are preferably multi-armed or high-molecular weight and used for medical uses, for example, making coatings on medical devices. Macromers of N-vinylpyrrolidone are also disclosed herein. | 11-10-2011 |
Parvenkumar Luthra, Gujarat IN
| Patent application number | Description | Published |
|---|---|---|
| 20100105889 | PROCESS FOR THE PREPARATION OF PENTOSAN POLYSULFATE OR SALTS THEREOF - A process for the preparation of Pentosan polysulfate sodium comprising a step of purifying depolymerized crude Pentosan polysulfate sodium by filtration through NF membrane system. | 04-29-2010 |
Parven Kumar Luthra, Vadodara IN
| Patent application number | Description | Published |
|---|---|---|
| 20100113798 | PROCESS FOR PREPARATION OF IRBESARTAN - A process for the preparation of Irbesartan of formula (I) using the step of, | 05-06-2010 |
| 20100179332 | PROCESS FOR THE PURIFICATION OF ROPINIROLE HYDROCHLORIDE - The present invention provides an improved process for the purification of ropinirole hydrochloride. The process includes (i) treating ropinirole hydrochloride with sodium dithionate and charcoal in suitable alcoholic solvent; (ii) triturating the ropinirole hydrochloride obtained in step (i) with ethanol; (iii) reacting the triturated solid with base in water immiscible solvent and isolating the free base; and (iv) treating the free base obtained in step (iii) with ethanolic HCl to give ropinirole hydrochloride. | 07-15-2010 |
| 20100249433 | PROCESS FOR THE PURIFICATION OF ROPINIROLE HYDROCHLORIDE - An improved process is described for the purification of ropinirole hydrochloride. The process includes (i) dissolving ropinirole hydrochloride in water; (ii) treating the solution obtained in step (i) with sodium dithionate and charcoal; (iii) treating the filtrate obtained in step (ii) with water immiscible solvent and base and isolating the free base; and (iv) treating the free base obtained in step (iii) with ethanolic HCl to give ropinirole hydrochloride. | 09-30-2010 |
Parven Kumar Luthra, Gujarat IN
| Patent application number | Description | Published |
|---|---|---|
| 20090312538 | PROCESS FOR THE PREPARATION OF SUCRALOSE OF HIGH PURITY - The present invention relates to an improved process for the preparation of Sucralose having purity of at least 99.6% comprising steps of | 12-17-2009 |
| 20100234632 | PROCESS FOR THE PREPARATION OF ENTACAPONE - The present invention relates to an improved process for the preparation of Entacapone of formula (I) | 09-16-2010 |
Sajinder Luthra, London GB
| Patent application number | Description | Published |
|---|---|---|
| 20090274603 | NON-AQUEOUS EXTRACTION OF [18F] FLUORIDE FROM CYCLOTRON TARGETS - The present invention provides a method and an apparatus for extracting an isotope from a gas. More specifically, the present invention depicts a system that has been devised which provides [ | 11-05-2009 |
Sajinder Kaur Luthra, London GB
| Patent application number | Description | Published |
|---|---|---|
| 20080213174 | Radiolabelled Insulin - The invention relates to in vivo imaging agents, specifically radiolabelled insulin derivatives of formula (III); wherein X is —CO—NH—, —NH—, —O—, —NHCONH—, or —NHCSNH—, and is preferably —CO—NH—, —NH— or —O—; Y is H, alkyl or aryl substituents; R* is a radiolabel moiety suitable for detection by SPECT or PET; and methods for preparing the same as well as their use in in vivo imaging methods. | 09-04-2008 |
| 20090220420 | TETRACYCLIC INDOLE DERIVATIVES AS IN VIVO IMAGING AGENTS AND HAVING PERIPHERALBENZODIAZEPINE RECEPTOR AFFINITY (PBR) - The present invention provides novel tetracyclic indole compounds of Formula (I) either as in vivo imaging agents or as therapeutic agents. A method for the preparation of the in vivo imaging agent compound is also provided by the invention, as well as a precursor for use in said method. Pharmaceutical compositions comprising the compounds of the invention are additionally provided. Where the pharmaceutical composition comprises a compound suitable for in vivo imaging, a kit is provided for the preparation of the pharmaceutical composition. In a further aspect, use of the compound for in vivo imaging or treatment of conditions associated with PBR is provided. | 09-03-2009 |
Vinod Luthra, Zoetermeer NL
| Patent application number | Description | Published |
|---|---|---|
| 20100067524 | Method and system for selecting a data transmission rate - A method and system for selecting a data transmission rate in a broadband network. The broadband network is connected to an access network for providing access for user equipment to the broadband network. Rate information is received from the user equipment. The rate information comprises a rate for transmitting data over the access network. Thereafter, a rate for transmitting data over the broadband network is selected. The selected rate for the broadband network is preferably less than or substantially equal to the rate for transmitting data over the access network. | 03-18-2010 |
Yogesh Luthra, Chavannes-Pres-Renens CH
| Patent application number | Description | Published |
|---|---|---|
| 20100271857 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line. | 10-28-2010 |
| 20100271858 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE HAVING GANGED CARRIER INJECTION LINES - Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region coupled to a bit line and a second region coupled to a source line. The apparatus may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The apparatus may further comprise a third region coupled to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region. | 10-28-2010 |
| 20110007578 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region. | 01-13-2011 |
| 20110019481 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device including the steps of applying a first non-negative voltage potential to a first region via a bit line and applying a second non-negative voltage potential to a second region via a source line. The method may also include applying a third voltage potential to a word line, wherein the word line may be spaced apart from and capacitively to a body region that may be electrically floating and disposed between the first region and the second region. The method may further include applying a fourth positive voltage potential to a third region via a carrier injection line, wherein the third region may be disposed below at least one of the first region, the body region, and the second region. | 01-27-2011 |
| 20110141836 | TECHNIQUES FOR REDUCING IMPACT OF ARRAY DISTURBS IN A SEMICONDUCTOR MEMORY DEVICE - Techniques for reducing impact of array disturbs in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for reducing impact of array disturbs in a semiconductor memory device by increasing the refresh rate to the semiconductor memory device based at least in part on a frequency of active operations. The method may comprise receiving a first refresh command including a first subarray address to perform a first refresh operation to a first logical subarray of memory cells associated with the first subarray address. The method may also comprise receiving a second refresh command including a second subarray address to perform a second refresh operation to a second logical subarray of memory cells associated with the second subarray address, wherein the second refresh command is received after a time period from the reception of the first refresh command. The method may further comprise performing a number of concurrent refresh operations during the time period. | 06-16-2011 |
| 20110273941 | TECHNIQUES FOR REFRESHING A SEMICONDUCTOR MEMORY DEVICE - Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line and a second region coupled to a carrier injection line. Each memory cell may also include a body region capacitively coupled to at least one word line and disposed between the first region and the second region and a decoupling resistor coupled to at least a portion of the body region. | 11-10-2011 |