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Luo, San Jose

An Luo, San Jose, CA US

Patent application numberDescriptionPublished
20100234752EEG control of devices using sensory evoked potentials - An EEG control of devices using Sensory Evoked Potentials (SEPs) (e.g., visually-evoked potentials), is disclosed. In some embodiments, a system receives a plurality of EEG signal samples; generates a stimulus locked average signal using the plurality of EEG signal samples; and determines whether the plurality of EEG signal samples are evoked in response to a pattern of stimulus.09-16-2010
20110040202SENSORY-EVOKED POTENTIAL (SEP) CLASSIFICATION/DETECTION IN THE TIME DOMAIN - Techniques are disclosed for sensory-evoked potential (SEPs, e.g., visual-evoked potentials) signal detection/classification by synchronizing EEG to the repeated presentation of sensory stimuli in the time domain. In some embodiments, a system receives a plurality of EEG signal samples, generates a stimulus-locked EEG and determines whether the plurality of EEG signal samples are evoked in response to a pattern of stimulus. In some embodiments, no prior knowledge about the update pattern (such as the flashing frequency of a visual stimulus) of the stimulus and no prior knowledge about an individual user's EEG pattern are required.02-17-2011

Falong Luo, San Jose, CA US

Patent application numberDescriptionPublished
20090313029Method And System For Backward Compatible Multi Channel Audio Encoding and Decoding with the Maximum Entropy - A method and system for backward compatible multi-channel audio encoding and decoding in sense of the space information maximum entropy is disclosed. The technical solution according to the invention can adopt any existing stereo channel encoding system to encode the multi-channels audio signals, so as to transmit the multi-channel audio signals at the low bit rate as that of the stereo audio signals. More importantly, the existing stereo channel reproducing systems can also decode the audio format that is encoded utilizing the encoding method according to the invention.12-17-2009

Haiyun Luo, San Jose, CA US

Patent application numberDescriptionPublished
20080198824SYSTEM AND METHOD FOR QOS PROVISIONING IN BROADBAND WIRELESS MESH NETWORKS - A method and system for QoS provisioning in broadband wireless mesh networks are disclosed. According to one embodiment, a computer-implemented method, comprises providing a dual mode mesh router having a plurality of radios, wherein the mesh router is used in a cell of a plurality of cells that covers a geographic region. The mesh router includes one or more WiMAX backhaul radios, one or more WiFi backhaul radios, one or more WiMAX access radios, one or more WiFi access radios, and three or more intra-mesh radios. Traffic is received at the dual mode mesh router. A minimum quality of service requirement is identified for the traffic. The traffic is routed via the one or more WiMAX backhaul radio when the minimum quality of service meets a predetermined value.08-21-2008
20090187983METHOD AND SYSTEM FOR DISTRIBUTED, LOCALIZED AUTHENTICATION IN THE FRAMEWORK OF 802.11 - A method for controlling Internet access of a mobile device by using a communication system having a number of access points includes the steps of performing a certificate-based authentication between an authentication access point and a mobile device seeking access to the Internet; transmitting a certificate from the mobile device to the authentication access point; verifying the certificate by the authentication access point; determining whether the authenticating mobile device's certificate has been revoked prior to the expiration of its lifetime; and granting the authenticating mobile device access to the Internet, if the certificate has been verified successfully and not revoked prior to the expiration of its lifetime.07-23-2009
20100027464Method & apparatus for minimizing packet transmission loss in a wireless network - A wireless communication device, such as a wireless router or access point, transmits and receives signals according any one of several standard or proprietary wireless protocols and automatically adapts its transmission rate according to the condition of a link or channel over which it is sending and receiving signals. A packet delay value is used to calculate the maximum number of packet retransmissions that are acceptable given a particular application. The packet retransmission value is used to calculate a maximum acceptable packet loss value which is then compared against actual packet losses to determine whether or not to change the packet transmission rate. If it is determined that the actual packet losses are less than the maximum acceptable value, then the packet transmission rate can be changed to a higher rate and if it is determined that the actual packet losses are greater than the maximum acceptable value, then the packet transmission rate can be changed to be a lower rate.02-04-2010

Patent applications by Haiyun Luo, San Jose, CA US

Hao Luo, San Jose, CA US

Patent application numberDescriptionPublished
20080315918Thin film transistor logic - A thin-film logic circuit, which can be fabricated entirely of TFTs of the same conductivity type, includes a logic stage connected to a supply voltage and a level shifter connected to a wider voltage range provided by the supply voltage and ground. The logic circuit produces output signals with full rail-to-rail signal range from ground to the supply voltage and can implement or include a basic logic component such as an inverter, a NAND gate, or a NOR gate or more complicated circuits in which many basic logic components are cascaded together. Such logic circuits can be fabricated directly on flexible structures or large areas such as in flat panel displays.12-25-2008
20100078640Thin Film Transistor Backplane - A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.04-01-2010

Hengbin Luo, San Jose, CA US

Patent application numberDescriptionPublished
20110106421NAVIGATION SYSTEM WITH SINGLE SELECTION MILEAGE SINGLE CAPTURE MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a navigation system includes: generating a travel route having a business location for displaying on a device; calculating a current location along the travel route; identifying a travel segment with the current location; calculating a travel distance for the travel segment; and verifying the travel distance based on where the business location is within the travel segment.05-05-2011

Jih-Shiuan Luo, San Jose, CA US

Patent application numberDescriptionPublished
20100002327METHOD FOR IMPROVING MAGNETIC READ SENSOR MANUFACTURING USING EXTERNAL AND/OR EMBEDDED HEATING ELEMENT - A method for testing a magnetic head to determine whether the magnetic head is unacceptably affected by temperature variations. The test includes testing the magnetic head at different temperatures and measuring either or both of a signal amplitude and a signal asymmetry of a signal from the magnetic head at the different temperatures. If signal amplitude or signal asymmetry vary excessively as a result of the temperature change then the head can be scrapped.01-07-2010

Patent applications by Jih-Shiuan Luo, San Jose, CA US

Leeshawn Luo, San Jose, CA US

Patent application numberDescriptionPublished
20090014853Integrated circuit package for semiconductior devices with improved electric resistance and inductance - A semiconductor integrated circuit package having a leadframe (01-15-2009

Lixiong Luo, San Jose, CA US

Patent application numberDescriptionPublished
20090256246SEMICONDUCTOR PACKAGING TECHNIQUES - A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.10-15-2009

Qi Luo, San Jose, CA US

Patent application numberDescriptionPublished
20080311690ELIMINATE RELEASE ETCH ATTACK BY INTERFACE MODIFICATION IN SACRIFICIAL LAYERS - Methods of making a microelectromechanical system (MEMS) device are described. In some embodiments, the method includes forming a sacrificial layer over a substrate, treating at least a portion of the sacrificial layer to form a treated sacrificial portion, forming an overlying layer over at least a part of the treated sacrificial portion, and at least partially removing the treated sacrificial portion to form a cavity situated between the substrate and the overlying layer, the overlying layer being exposed to the cavity.12-18-2008
20090212935Anti-collision Emergency Braking System - An anti-collision emergency braking system enables emergency information transferring from leading vehicle to trailing vehicle and enables emergency automatic braking. It comprises a central commanding element which takes input from a number of sensing elements and gives commands to other acting elements: a receiver which receives emergency signals from the leading vehicle, a transmitter which sends out emergency signals toward the trailing vehicle, an accelerometer which senses the acceleration extents of the present vehicle, an automatic braking element which applies certain amount of braking power after receiving the commands from the central commanding element, and one or more warning elements.08-27-2009
20090257105DEVICE HAVING THIN BLACK MASK AND METHOD OF FABRICATING THE SAME - A thin black mask is created using a single mask process. A dielectric layer is deposited over a substrate. An absorber layer is deposited over the dielectric layer and a reflector layer is deposited over the absorber layer. The absorber layer and the reflector layer are patterned using a single mask process.10-15-2009

Qian Luo, San Jose, CA US

Patent application numberDescriptionPublished
20100096273CU SURFACE PLASMA TREATMENT TO IMPROVE GAPFILL WINDOW - A method and apparatus for selectively controlling deposition rate of conductive material during an electroplating process. Dopants are predominantly incorporated into a conductive seed layer on field regions of a substrate prior to filling openings in the field regions by electroplating. A substrate is positioned in one or more processing chambers, and barrier and conductive seed layers formed. A dopant precursor is provided to the chamber and ionized, with or without voltage bias. The dopant predominantly incorporates into the conductive seed layer on the field regions. Electrical conductivity of the conductive seed layer on the field regions is reduced relative to that of the conductive seed layer in the openings, resulting in low initial deposition rate of metal on the field regions during electroplating, and little or no void formation in the metal deposited in the openings.04-22-2010

Xiaodong Luo, San Jose, CA US

Patent application numberDescriptionPublished
20090059048IMAGE SENSOR WITH HIGH DYNAMIC RANGE IN DOWN-SAMPLING MODE - An image sensor has an array of photo-sensitive pixels and supports a line-by-line read out of rows. In a normal resolution each row has the same nominal gain and exposure time. In a down-sampling mode the exposure times of the rows are varied according to an alternating sequence having at least two different exposure times. During down-sampling, raw pixel data from rows with different exposure times is combined to simultaneously achieve down-sampling and a high dynamic range.03-05-2009
20090109305One-step black level calibration for image sensors - Embodiments of a process comprising receiving a plurality of offset analog signals, each corresponding to one of a plurality of black pixels in a pixel array; obtaining a corresponding digital value for each offset analog signal; computing an average of the digital values; and computing a black-level offset that, if applied to the digital values, would make the average of the digital values equal to a target value. Also disclosed are embodiments of an apparatus comprising an analog-to-digital converter coupled to an analog channel to receive offset analog black pixel signals from the analog channel and to obtain a corresponding digital value for each offset analog signal; circuitry and logic coupled to the analog-to-digital converter to average the digital values corresponding to the black pixels and compute a black-level offset that, if applied to the digital values of the black pixels, would make the average of the digital values of the black pixels equal to a target value.04-30-2009

Yuhao Luo, San Jose, CA US

Patent application numberDescriptionPublished
20090108337Method of and circuit for protecting a transistor formed on a die - A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.04-30-2009
20110061711BUILDING-INTEGRATED SOLAR PHOTOVOLTAIC PANEL - A device to generate electricity from solar rays is provided. A photovoltaic solar cell unit comprises a first cover and a second cover. The second cover is generally parallel to the first cover and the second cover is spaced from the first cover. The first and the second cover have a longitudinal axis. The photovoltaic solar cell unit also includes a solar cell disposed between the first cover and the second cover with the solar cell being disposed at a predetermined angle relative to the longitudinal axis.03-17-2011
20110065226METHOD TO BREAK AND ASSEMBLE SOLAR CELLS - The present disclosure relates generally to a method to break and assemble solar cells to make solar panel. The present disclosure provides a method to produce solar pieces from solar cell, as well as assemble them together. The present disclosure device is unique when compared with other known devices and solutions because the present disclosure provides a high speed method to break scribed cells into pieces. A method of forming a string of solar cells includes providing a scribe line on a solar cell and placing a first ribbon on the solar cell. The method then includes placing the solar cell on a supporter and then breaking the solar cell into a plurality of solar cell pieces. The method then has the step of placing a second ribbon on the solar cell pieces and soldering the first and second ribbons and the solar cell pieces and then assembling the solar cell pieces into a string of solar cells.03-17-2011
20110088743METHOD TO MANAGE A PHOTOVOLTAIC SYSTEM - An apparatus and method relates to managing and controlling a photovoltaic system, especially for the safety, maintenance, alert of theft, and connection failure of the system. It is more specially for cases during the night time when the panel is not generating electricity. The present disclosure provides: an AC panel, an inverter; a communication circuit in a panel inverter to send and receive signals, a control circuit, a communicator and a power line communication method between communicator and panel inverters. The communicator detects an identification of each panel to identify the panels and collect data from each panel. The communicator is connected to the Internet through a web gateway. The apparatus also has a web based managing system to collect data from the communicator, as well as transmit signals to the communicator.04-21-2011
20110090089METHOD AND APPARATUS FOR DETECTING A FAULT IN A SOLAR CELL PANEL AND AN INVERTER - A method and apparatus for detecting a fault of a solar panel and an inverter in a solar array includes a monitoring device to detect and to identify a fault of a solar panel and an inverter in a solar array. The method generates a normal operation profile by extracting median values of operation profiles from multiple solar panels in a solar array and then compares an individual operation profile against a normal profile to determine a fault in a solar panel. The method and apparatus can detect a fault in a combination of solar panel and inverter and can identify a fault in an inverter. The method and apparatus can store faulty profiles in a database for particular faults in a solar panel. The method and apparatus can then compare an operation profile from a faulty solar panel with a number of faulty profiles in a database to identify the type of the fault and then generate and report the fault and suggest corrective action.04-21-2011