Patent application number | Description | Published |
20080222640 | Prediction Based Priority Scheduling - Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing. | 09-11-2008 |
20090006886 | SYSTEM AND METHOD FOR ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM - A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure. | 01-01-2009 |
20090006900 | SYSTEM AND METHOD FOR PROVIDING A HIGH FAULT TOLERANT MEMORY SYSTEM - A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure. | 01-01-2009 |
20090049365 | SYSTEM AND METHOD FOR PROVIDING ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM - A system and method for providing error correction and detection in a memory system. The memory system includes a plurality of memory devices, and error detection and correction logic. The error detection and correction logic includes instructions for generating an error correction code (ECC) word that includes bits from two more of the memory devices and from different memory device transfers. | 02-19-2009 |
20090063759 | SYSTEM AND METHOD FOR PROVIDING CONSTRAINED TRANSMISSION AND STORAGE IN A RANDOM ACCESS MEMORY - A system and method for providing constrained transmission and storage in a random access memory. A system includes a memory device for providing constrained transmission and storage. The memory device includes an interface to a data bus, the data bus having a previous state. The memory device also includes an interface to an address and command bus for receiving a request to read data at an address, and a mechanism for initiating a programmable mode. The programmable mode facilitates retrieving data at the address, and executing an exclusive or (XOR) using the retrieved data and the previous state of the data bus as input. The result of the XOR operation is transmitted to the requester via the data bus. | 03-05-2009 |
20090063896 | SYSTEM AND METHOD FOR PROVIDING DRAM DEVICE-LEVEL REPAIR VIA ADDRESS REMAPPINGS EXTERNAL TO THE DEVICE - A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line. | 03-05-2009 |
20090216985 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DYNAMIC SELECTIVE MEMORY MIRRORING - Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory. | 08-27-2009 |
20090254705 | BUS ATTACHED COMPRESSED RANDOM ACCESS MEMORY - A computer memory system having a three-level memory hierarchy structure is disclosed. The system includes a memory controller, a volatile memory, and a non-volatile memory. The volatile memory is divided into an uncompressed data region and a compressed data region. | 10-08-2009 |
20100180179 | PROTECTING AND MIGRATING MEMORY LINES - A data protection method is provided. The method includes receiving data; generating compressed data based on the data; determining a degree of compressibility based on the compressed data; determining an amount of free space based on the degree of compressibility; and setting one or more error bits based on the amount of free space. | 07-15-2010 |
20100214829 | MEMORY PROGRAMMING - Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range. | 08-26-2010 |
20100217915 | HIGH AVAILABILITY MEMORY SYSTEM - A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks. | 08-26-2010 |
20100218070 | LENGTHENING LIFE OF A LIMITED LIFE MEMORY - A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells, including at least a first group with at least one cell. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way (the cells can be PCM or another technology). Each one of the storage cells is arbitrarily individually changeable among the at least two levels, and each of the cells is cost-asymmetric. A controller encodes the identical message in the at least first group using the first way or the second way, based on which way incurs a least cost when writing the message into the at least one cell of the at least first group, given current levels of the at least first group. | 08-26-2010 |
20100218071 | WRITING A SPECIAL SYMBOL TO A MEMORY TO INDICATE THE ABSENCE OF A DATA SIGNAL - A method for writing in a memory system that includes receiving an address corresponding to a memory location in a memory, receiving a desired content to be written, encoding the desired content into a symbol, and writing the symbol to the memory location using an iterative write process of at least one write and one read to the memory location. The iterative write process includes determining if the symbol was successfully written to the memory location and exiting the iterative write process in response to the symbol being successfully written to the memory location. The iterative write process also includes determining if a halt condition has been met and exiting the iterative write process if the halt condition has been met. Once the iterative write process has been exited, the memory location may be identified as a candidate for being written with a special symbol. | 08-26-2010 |
20100287436 | System for Error Decoding with Retries and Associated Methods - A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue. | 11-11-2010 |
20100287445 | System to Improve Memory Reliability and Associated Methods - A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure. | 11-11-2010 |
20100287454 | System to Improve Error Code Decoding Using Historical Information and Associated Methods - A system to improve error code decoding using historical information may include storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system may also generate a memory rank score for each memory rank. The system may also include an error control decoder that may use the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not. | 11-11-2010 |
20100293436 | System for Error Control Coding for Memories of Different Types and Associated Methods - A system to improve error control coding may include memory chips of at least two different kinds. The system may also include error control encoder circuitry to substantially encode data for storage in any memory rank. The system may further include error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder. | 11-18-2010 |
20100293437 | System to Improve Memory Failure Management and Associated Methods - A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to. | 11-18-2010 |
20100293438 | System to Improve Error Correction Using Variable Latency and Associated Methods - A system to improve error correction may include a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system may also include a slow decoder to possibly correct the uncorrectable error in a data packet based upon the at least two data packets. | 11-18-2010 |
20100299576 | System to Improve Miscorrection Rates in Error Control Code Through Buffering and Associated Methods - A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal. | 11-25-2010 |
20110228600 | MEMORY PROGRAMMING - Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range. | 09-22-2011 |
20110246703 | CONSTRAINED CODING TO REDUCE FLOATING GATE COUPLING IN NON-VOLATILE MEMORIES - Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword. | 10-06-2011 |
20110252215 | COMPUTER MEMORY WITH DYNAMIC CELL DENSITY - A computer memory with dynamic cell density including a method that obtains a target size for a first memory region. The first memory region includes first memory units operating at a first density. The first memory units are includes in a memory in a memory system. The memory is operable at the first density and a second density. The method also includes: determining that a current size of the first memory region is not within a threshold of the target size and that the first memory region is smaller than the target size; identifying a second memory unit currently operating at the second density in a second memory region, the second memory unit included in the memory; and dynamically reassigning, during normal system operation, the second memory unit into the first memory region, the second memory unit operating at the first density after being reassigned to the first memory region. | 10-13-2011 |
20110307670 | ENCODING DATA INTO CONSTRAINED MEMORY - Encoding data into constrained memory using a method for writing data that includes receiving write data to be encoded into a write word, receiving constraints on symbol values associated with the write word, encoding the write data into the write word, and writing the write word to a memory. The encoding includes: representing the write data and the constraints as a first linear system in a first field of a first size; embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size; solving the second linear system in the second field resulting in a solution; and collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values associated with the write word. | 12-15-2011 |
20110320864 | HETEROGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM - Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing in response to the removing any stale data being complete. | 12-29-2011 |
20110320869 | HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM - Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels. | 12-29-2011 |
20110320872 | HIERARCHICAL ERROR INJECTION FOR COMPLEX RAIM/ECC DESIGN - A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined. | 12-29-2011 |
20110320881 | ISOLATION OF FAULTY LINKS IN A TRANSMISSION MEDIUM - Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link. | 12-29-2011 |
20110320911 | Computer System and Method of Protection for the System's Marking Store - A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out. | 12-29-2011 |
20110320914 | ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM - Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure. | 12-29-2011 |
20110320918 | ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM - Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations. | 12-29-2011 |
20110320921 | FAILING BUS LANE DETECTION USING SYNDROME ANALYSIS - Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus. | 12-29-2011 |
20120127790 | ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES - Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin includes one or more of the values. A group of bins are identified, the group of bins are among the possible bins with associated costs that are within a threshold of the target cost. A maximum number of bins are selected from the group of bins that have non-overlapping values. The selected bins are stored along with the values of the selected bins utilized to encode and decode contents of the analog memory. | 05-24-2012 |
20120131304 | Adaptive Wear Leveling via Monitoring the Properties of Memory Reference Stream - Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses. | 05-24-2012 |
20120144272 | PROBABILISTIC MULTI-TIER ERROR CORRECTION IN NOT-AND (NAND) FLASH MEMORY - Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output. | 06-07-2012 |
20120173936 | CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS - Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold. | 07-05-2012 |
20120180060 | PREDICTION BASED PRIORITY SCHEDULING - Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing. | 07-12-2012 |
20120204071 | WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES - Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses. | 08-09-2012 |
20120218814 | WRITE BANDWIDTH IN A MEMORY CHARACTERIZED BY A VARIABLE WRITE TIME - A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays. | 08-30-2012 |
20120290778 | INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS - Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector. The virtual write vectors are combined into a write word and the write word is output to the block of memory cells. | 11-15-2012 |
20120311262 | MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE - Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state. | 12-06-2012 |
20130013860 | MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE - Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting. | 01-10-2013 |
20130013886 | ADAPTIVE WEAR LEVELING VIA MONITORING THE PROPERTIES OF MEMORY REFERENCE STREAM - Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses. | 01-10-2013 |
20130018889 | Lossless compression of high nominal-range dataAANM Jagmohan; AshishAACI IrvingtonAAST NYAACO USAAGP Jagmohan; Ashish Irvington NY USAANM Knight; Joshua W.AACI Mohegan LakeAAST NYAACO USAAGP Knight; Joshua W. Mohegan Lake NY USAANM Lastras-Montano; Luis A.AACI Cortlandt ManorAAST NYAACO USAAGP Lastras-Montano; Luis A. Cortlandt Manor NY US - A method for receiving a data stream that includes data samples, each data sample having one of a plurality of actual values. For each data sample in the data stream, a first index in a dictionary is selected. The dictionary includes indices corresponding to each of the plurality of actual values. The first index corresponds to an actual value of the data sample. A predicted value of the data sample is generated in response to previously received data samples in the data stream and to a prediction algorithm. A second index in the dictionary that corresponds to an actual value in the dictionary that is closest to the value of the predicted value is selected. The difference between the first index and the second index is calculated and compressed. The compressed difference between the first index and the second index is then output. This process is performed for each data sample in the data stream. | 01-17-2013 |
20130019029 | LOSSLESS COMPRESSION OF A PREDICTIVE DATA STREAM HAVING MIXED DATA TYPESAANM Jagmohan; AshishAACI IrvingtonAAST NYAACO USAAGP Jagmohan; Ashish Irvington NY USAANM Lastras-Montano; Luis A.AACI Cortlandt ManorAAST NYAACO USAAGP Lastras-Montano; Luis A. Cortlandt Manor NY US - Lossless compression of a data stream having mixed data types, including a method for receiving a data stream that includes a plurality of different types of bit groups. Bit groups of at least two different types are extracted from the data stream to form a sub-stream. Circular shifts of the sub-stream are generated and then sorted into a sorted list of circular shifts. A transformed string that includes a bit group from each of the circular shifts is extracted from the sorted list of circular shifts. A location in the transformed string of a bit group from a pre-determined location in the sub-stream is identified. The transformed string is partitioned between the at least two different types of bit groups into transformed string partitions, and the transformed string partitions are compressed to form compressed transformed string partitions. The compressed transformed string partitions and the location are output. | 01-17-2013 |
20130031324 | PROTECTING AND MIGRATING MEMORY LINES - A data protection method is provided that includes determining a compressibility score of one or more lines of data stored in a memory. The memory includes a first area characterized by a first reliability level and a second area characterized by a second reliability level. Lines of data with a first compressibility score are migrated to the first area of the memory. Lines of data with a second compressibility score are migrated to the second area of the memory. | 01-31-2013 |
20130047040 | CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS - Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold. | 02-21-2013 |
20130191682 | HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM - A computer implemented method for providing homogeneous recovery in a redundant memory system. The method includes receiving a notification that a memory channel has failed, where the memory channel is one of a plurality of memory channels in a memory system. New operations are blocked from starting on the memory channels in response to the notification, and any pending operations on the memory channels are completed in response to the notification. A recovery operation is performed on the memory channels in response to the completing. The new operations are started on at least a first subset of the memory channels in response to the recovery operation completing. The memory system is configured to operate with the first subset of the memory channels. | 07-25-2013 |
20130191683 | HETEROGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM - Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing based on the removing any stale data being complete. | 07-25-2013 |
20130191685 | PER-RANK CHANNEL MARKING IN A MEMORY SYSTEM - Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices. The memory system is configured to perform a method that includes determining that more than a threshold number of memory devices in the first group are failing. An error correction code (ECC) is configured to compensate for errors associated with memory devices in the first group on the memory channel and to perform error correction on errors associated with memory devices in the second group on the memory channel. | 07-25-2013 |
20130191698 | HIERARCHICAL CHANNEL MARKING IN A MEMORY SYSTEM - Channel marking is provided in a memory system that includes a first memory channel, a second memory channel, and error correction code (ECC) logic. The memory system is configured to perform a method that includes receiving a request to apply a first channel mark to the first memory channel and determining a priority level of the first channel mark. A request is received to apply a second channel mark to the second memory channel, and a priority level of the second mark is determined. It is determined that the priority level of the first channel mark is higher than the priority level of the second channel mark. The first channel mark is supplied to the ECC logic while blocking the second channel mark from the ECC logic. | 07-25-2013 |
20130212427 | RECLAIMING DISCARDED SOLID STATE DEVICES - Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced. | 08-15-2013 |
20130227582 | Prediction Based Priority Scheduling - Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing. | 08-29-2013 |
20130318423 | MIS-CORRECTION AND NO-CORRECTION RATES FOR ERROR CONTROL - An embodiment is a method for encoding data with an error correction code. The method includes receiving a first number of data symbols by a memory controller, receiving a second number of meta-data sub-symbols, generating a third number of check symbols using an ECC, where the third number includes a difference between a number of symbols in an ECC codeword and the first number and generating a mismatch vector from the check and meta-data sub-symbols, where a number of sub-symbols of the mismatch vector includes the second number. The method also includes generating an adjustment syndrome symbol by multiplying the mismatch vector by a matrix, generating the third number of adjusted check symbols responsive to the adjustment syndrome symbol, and generating a final codeword by concatenating the adjusted check symbols and the data symbols, where the final codeword includes the number of symbols in the ECC codeword. | 11-28-2013 |
20140006897 | CORRECTION OF STRUCTURED BURST ERRORS IN DATA | 01-02-2014 |
20140101481 | PER-RANK CHANNEL MARKING IN A MEMORY SYSTEM - Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices. The memory system is configured to perform a method that includes determining that more than a threshold number of memory devices in the first group are failing. An error correction code (ECC) is configured to compensate for errors associated with memory devices in the first group on the memory channel and to perform error correction on errors associated with memory devices in the second group on the memory channel. | 04-10-2014 |
20140164692 | MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING - This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data. | 06-12-2014 |
20140164820 | MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING - This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data. | 06-12-2014 |
20140164871 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 06-12-2014 |
20140164874 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 06-12-2014 |
20140185397 | HYBRID LATCH AND FUSE SCHEME FOR MEMORY REPAIR - A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element. | 07-03-2014 |
20140185398 | HYBRID LATCH AND FUSE SCHEME FOR MEMORY REPAIR - A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element. | 07-03-2014 |
20140195765 | IMPLEMENTING USER MODE FOREIGN DEVICE ATTACHMENT TO MEMORY CHANNEL - A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space. The storage capacity on the device is doubly mapped in the address space creating separate control and data address spaces to allow user mode processes to control the device therefore eliminating the need for software system calls. A processor Memory Management Unit (MMU) coordinates multiple user processes accessing the device registers and buffers providing address space protection of each of interfaces, shifting device protection to the processor MMU from system software. | 07-10-2014 |
20140223117 | SECURING THE CONTENTS OF A MEMORY DRIVE - A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device. | 08-07-2014 |
20140223120 | SECURING THE CONTENTS OF A MEMORY DEVICE - A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device. | 08-07-2014 |
20140365480 | PERSONALIZED LOW LATENCY COMMUNICATION - Embodiments relate to personalized low latency communications. A method may include receiving a description of content of a message, receiving recipient data corresponding to at least two possible recipients within a population of possible recipients, and selecting a relevant subpopulation of the population. The selecting may include, for each of the at least two possible recipients, ranking a strength of an indirect relationship between the description and the recipient data. The indirect relationship may be based on the description, the recipient data and at least one additional data source. The selecting may also include, for each of the at least two possible recipients, adding a possible recipient to the relevant subpopulation based on the ranking of the indirect relationship associated with the possible recipient. The method may further include initiating a two-way communication channel between a sender of the message and the relevant subpopulation. | 12-11-2014 |
20140365503 | ESTIMATION OF CLOSENESS OF TOPICS BASED ON GRAPH ANALYTICS - Embodiments relate to estimating closeness of topics based on graph analytics. A graph that includes a plurality of nodes and edges is accessed. Each node in the graph represents a topic and each edge represents a known association between two topics. A statistical traversal experiment is performed on the graph. A strength of relations between any two topics represented by nodes in the graph is inferred based on statistics extracted from the statistical traversal experiment. | 12-11-2014 |
20140365504 | ESTIMATION OF CLOSENESS OF TOPICS BASED ON GRAPH ANALYTICS - Embodiments relate to estimating closeness of topics based on graph analytics. A graph that includes a plurality of nodes and edges is accessed. Each node in the graph represents a topic and each edge represents a known association between two topics. A statistical traversal experiment is performed on the graph. A strength of relations between any two topics represented by nodes in the graph is inferred based on statistics extracted from the statistical traversal experiment. | 12-11-2014 |
20140365584 | PERSONALIZED LOW LATENCY COMMUNICATION - Embodiments relate to personalized low latency communications. A method may include receiving a description of content of a message, receiving recipient data corresponding to at least two possible recipients within a population of possible recipients, and selecting a relevant subpopulation of the population. The selecting may include, for each of the at least two possible recipients, ranking a strength of an indirect relationship between the description and the recipient data. The indirect relationship may be based on the description, the recipient data and at least one additional data source. The selecting may also include, for each of the at least two possible recipients, adding a possible recipient to the relevant subpopulation based on the ranking of the indirect relationship associated with the possible recipient. The method may further include initiating a two-way communication channel between a sender of the message and the relevant subpopulation. | 12-11-2014 |
20150089279 | IMPLEMENTING MEMORY MODULE COMMUNICATIONS WITH A HOST PROCESSOR IN MULTIPORTED MEMORY CONFIGURATIONS - A method, system and computer program product are provided for implementing ECC (Error Correction Codes) memory module communications with a host processor in multi-ported memory configurations in a computer system. Each of multiple memory modules operating in unison is enabled to identify which memory module is the one required to communicate module specific information back to the host processor. All of the multiple memory modules operating in unison are enabled to generate back to the host processor a valid ECC word, while other multiple memory modules individually being unaware of data contents of the one memory module required to communicate back to the processor. | 03-26-2015 |