Patent application number | Description | Published |
20090027165 | SYSTEMS AND METHODS FOR OBJECT LOCALIZATION AND PATH IDENTIFICATION BASED ON RFID SENSING - A networked radio frequency identification system includes a plurality of radio frequency identification (RFID) tag readers, a computer in signal communication with the RFID tag readers over a network, and a software module for storage on and operable by the computer that localizes RFID tags based on information received from the RFID tag readers using a network model having endpoints and oriented links. In an additional example, at least one of the RFID tag readers includes an adjustable configuration setting selected from RF signal strength, antenna gain, antenna polarization, and antenna orientation. In a further aspect, the system localizes RFID tags based on hierarchical threshold limit calculations. In an additional aspect, the system controls a locking device associated with an access point based on localization of an authorized RFID tag at the access point and reception of additional authorizing information from an input device. | 01-29-2009 |
20090027203 | SYSTEMS AND METHODS FOR OBJECT LOCALIZATION AND PATH IDENTIFICATION BASED ON RFID SENSING - A networked radio frequency identification system includes a plurality of radio frequency identification (RFID) tag readers, a computer in signal communication with the RFID tag readers over a network, and a software module for storage on and operable by the computer that localizes RFID tags based on information received from the RFID tag readers using a network model having endpoints and oriented links. In an additional example, at least one of the RFID tag readers includes an adjustable configuration setting selected from RF signal strength, antenna gain, antenna polarization, and antenna orientation. In a further aspect, the system localizes RFID tags based on hierarchical threshold limit calculations. In an additional aspect, the system controls a locking device associated with an access point based on localization of an authorized RFID tag at the access point and reception of additional authorizing information from an input device. | 01-29-2009 |
20110109441 | SYSTEMS AND METHODS FOR OBJECT LOCALIZATION AND PATH IDENTIFICATION BASED ON RFID SENSING - A networked radio frequency identification system includes a plurality of radio frequency identification (RFID) tag readers, a computer in signal communication with the RFID tag readers over a network, and a software module for storage on and operable by the computer that localizes RFID tags based on information received from the RFID tag readers using a network model having endpoints and oriented links. In an additional example, at least one of the RFID tag readers includes an adjustable configuration setting selected from RF signal strength, antenna gain, antenna polarization, and antenna orientation. In a further aspect, the system localizes RFID tags based on hierarchical threshold limit calculations. In an additional aspect, the system controls a locking device associated with an access point based on localization of an authorized RFID tag at the access point and reception of additional authorizing information from an input device. | 05-12-2011 |
20130278382 | SYSTEMS AND METHODS FOR OBJECT LOCALIZATION AND PATH IDENTIFICATION BASED ON RFID SENSING - A networked radio frequency identification system includes a plurality of radio frequency identification (RFID) tag readers, a computer in signal communication with the RFID tag readers over a network, and a software module for storage on and operable by the computer that localizes RFID tags based on information received from the RFID tag readers using a network model having endpoints and oriented links. In an additional example, at least one of the RFID tag readers includes an adjustable configuration setting selected from RF signal strength, antenna gain, antenna polarization, and antenna orientation. In a further aspect, the system localizes RFID tags based on hierarchical threshold limit calculations. In an additional aspect, the system controls a locking device associated with an access point based on localization of an authorized RFID tag at the access point and reception of additional authorizing information from an input device. | 10-24-2013 |
20130278388 | SYSTEMS AND METHODS FOR OBJECT LOCALIZATION AND PATH IDENTIFICATION BASED ON RFID SENSING - A networked radio frequency identification system includes a plurality of radio frequency identification (RFID) tag readers, a computer in signal communication with the RFID tag readers over a network, and a software module for storage on and operable by the computer that localizes RFID tags based on information received from the RFID tag readers using a network model having endpoints and oriented links. In an additional example, at least one of the RFID tag readers includes an adjustable configuration setting selected from RF signal strength, antenna gain, antenna polarization, and antenna orientation. In a further aspect, the system localizes RFID tags based on hierarchical threshold limit calculations. In an additional aspect, the system controls a locking device associated with an access point based on localization of an authorized RFID tag at the access point and reception of additional authorizing information from an input device. | 10-24-2013 |
20130278389 | SYSTEMS AND METHODS FOR OBJECT LOCALIZATION AND PATH IDENTIFICATION BASED ON RFID SENSING - A networked radio frequency identification system includes a plurality of radio frequency identification (RFID) tag readers, a computer in signal communication with the RFID tag readers over a network, and a software module for storage on and operable by the computer that localizes RFID tags based on information received from the RFID tag readers using a network model having endpoints and oriented links. In an additional example, at least one of the RFID tag readers includes an adjustable configuration setting selected from RF signal strength, antenna gain, antenna polarization, and antenna orientation. In a further aspect, the system localizes RFID tags based on hierarchical threshold limit calculations. In an additional aspect, the system controls a locking device associated with an access point based on localization of an authorized RFID tag at the access point and reception of additional authorizing information from an input device. | 10-24-2013 |
20130278390 | SYSTEMS AND METHODS FOR OBJECT LOCALIZATION AND PATH IDENTIFICATION BASED ON RFID SENSING - A networked radio frequency identification system includes a plurality of radio frequency identification (RFID) tag readers, a computer in signal communication with the RFID tag readers over a network, and a software module for storage on and operable by the computer that localizes RFID tags based on information received from the RFID tag readers using a network model having endpoints and oriented links. In an additional example, at least one of the RFID tag readers includes an adjustable configuration setting selected from RF signal strength, antenna gain, antenna polarization, and antenna orientation. In a further aspect, the system localizes RFID tags based on hierarchical threshold limit calculations. In an additional aspect, the system controls a locking device associated with an access point based on localization of an authorized RFID tag at the access point and reception of additional authorizing information from an input device. | 10-24-2013 |
20140375429 | SYSTEMS AND METHODS FOR OBJECT LOCALIZATION AND PATH IDENTIFICATION BASED ON RFID SENSING - A networked radio frequency identification system includes a plurality of radio frequency identification (RFID) tag readers, a computer in signal communication with the RFID tag readers over a network, and a software module for storage on and operable by the computer that localizes RFID tags based on information received from the RFID tag readers using a network model having endpoints and oriented links. In an additional example, at least one of the RFID tag readers includes an adjustable configuration setting selected from RF signal strength, antenna gain, antenna polarization, and antenna orientation. In a further aspect, the system localizes RFID tags based on hierarchical threshold limit calculations. In an additional aspect, the system controls a locking device associated with an access point based on localization of an authorized RFID tag at the access point and reception of additional authorizing information from an input device. | 12-25-2014 |
20140375430 | SYSTEMS AND METHODS FOR OBJECT LOCALIZATION AND PATH IDENTIFICATION BASED ON RFID SENSING - A networked radio frequency identification system includes a plurality of radio frequency identification (RFID) tag readers, a computer in signal communication with the RFID tag readers over a network, and a software module for storage on and operable by the computer that localizes RFID tags based on information received from the RFID tag readers using a network model having endpoints and oriented links. In an additional example, at least one of the RFID tag readers includes an adjustable configuration setting selected from RF signal strength, antenna gain, antenna polarization, and antenna orientation. In a further aspect, the system localizes RFID tags based on hierarchical threshold limit calculations. In an additional aspect, the system controls a locking device associated with an access point based on localization of an authorized RFID tag at the access point and reception of additional authorizing information from an input device. | 12-25-2014 |
20140375431 | SYSTEMS AND METHODS FOR OBJECT LOCALIZATION AND PATH IDENTIFICATION BASED ON RFID SENSING - A networked radio frequency identification system includes a plurality of radio frequency identification (RFID) tag readers, a computer in signal communication with the RFID tag readers over a network, and a software module for storage on and operable by the computer that localizes RFID tags based on information received from the RFID tag readers using a network model having endpoints and oriented links. In an additional example, at least one of the RFID tag readers includes an adjustable configuration setting selected from RF signal strength, antenna gain, antenna polarization, and antenna orientation. In a further aspect, the system localizes RFID tags based on hierarchical threshold limit calculations. In an additional aspect, the system controls a locking device associated with an access point based on localization of an authorized RFID tag at the access point and reception of additional authorizing information from an input device. | 12-25-2014 |
20150130590 | SYSTEMS AND METHODS FOR OBJECT LOCALIZATION AND PATH IDENTIFICATION BASED ON RFID SENSING - A networked radio frequency identification system includes a plurality of radio frequency identification (RFID) tag readers, a computer in signal communication with the RFID tag readers over a network, and a software module for storage on and operable by the computer that localizes RFID tags based on information received from the RFID tag readers using a network model having endpoints and oriented links. In an additional example, at least one of the RFID tag readers includes an adjustable configuration setting selected from RF signal strength, antenna gain, antenna polarization, and antenna orientation. In a further aspect, the system localizes RFID tags based on hierarchical threshold limit calculations. In an additional aspect, the system controls a locking device associated with an access point based on localization of an authorized RFID tag at the access point and reception of additional authorizing information from an input device. | 05-14-2015 |
Patent application number | Description | Published |
20110102602 | Video Path Confirmation - There is disclosed a method, device, and system for verifying a video path between a source device and a destination device. The destination device may receive a video signal including at least one video test pattern from the source device via a network. The destination device may automatically judge that a video path exists if the received video signal meets at least one predetermined criteria. | 05-05-2011 |
20120294164 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR NON INTRUSIVE MEAN OPINION SCORE (MOS) ESTIMATION BASED ON PACKET LOSS PATTERN - Methods, systems, and computer readable media for non-intrusive mean opinion score (MOS) estimation based on packet loss pattern are disclosed. According to one aspect, a method for non-intrusive mean opinion score estimation based on packet loss pattern includes receiving a packet data stream, measuring the packet loss for the received data stream, calculating a probability of packet loss based on the measured packet loss, and calculating an estimated mean opinion score based on the calculated probability of packet loss. In one embodiment, the estimated mean opinion score is calculated using a mathematical function that maps calculated probability of packet loss to mean opinion score. In one embodiment, the mathematical function is a polynomial having coefficients that are selected so that the polynomial closely models reference opinion scores for a range of packet loss probabilities. In one embodiment, the coefficients are determined using a least squares analysis of a dataset that includes reference opinion scores for each of a range of packet loss probabilities. In one embodiment, the reference opinion scores for each of a range of packet loss probabilities are calculated using an intrusive algorithm to analyze lossy data streams that exhibit particular packet loss probabilities and generate mean opinion scores for each of the respective packet loss probabilities. | 11-22-2012 |
20130310959 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR UTILIZING A PLURALITY OF PRE-ENCODED PAYLOADS TO GENERATE A PACKET STREAM TRANSMISSION - Methods, systems, and computer readable media for utilizing a plurality of pre-encoded payloads in a stream transmission are disclosed. According to one aspect, a method includes receiving a plurality of payload streams associated with an audio stream clip file and selecting a first payload stream encoded at a first bit rate from the plurality of payload streams as the payload for a packet stream transmission being sent to a device under test. The method also includes receiving a bit rate change request that indicates a second payload stream encoded at a second bit rate is to be used as the payload for the packet stream transmission and conducting a synchronization procedure that synchronizes a first packet of the second payload stream with a last packet of the first payload stream in order to transition the packet stream transmission from the first bit rate to the second bit rate. | 11-21-2013 |
Patent application number | Description | Published |
20110004296 | Heart Valve Stent - A heart valve stent ( | 01-06-2011 |
20120010694 | CATHETER - The invention relates to a catheter ( | 01-12-2012 |
20120035703 | Truncated Conical Heart Valve Stent with Anchoring Threads and Methods of Use - A heart valve stent and methods of use thereof, such stent having a heart valve implant and several proximally disposed tissue anchors, also comprising a plurality of anchoring threads, each with a proximate end fastened to the stent or valve and a distal end attached to tissue within a heart chamber to provide tension between the heart chamber tissue and the stent. | 02-09-2012 |
20120035713 | Truncated Cone Heart Valve Stent - A heart valve stent having a section with a heart valve implant and several proximally disposed tissue anchors, also comprising a plurality of anchoring threats, each with a proximate end fastened to the stent or valve and a distal end attached to tissue within a heart chamber to provide tension between the heart chamber tissue and the stent. | 02-09-2012 |
20120283824 | Heart Valve Stent - A heart valve stent having a section equipped to receive a heart valve implant and several proximally disposed anchoring elements, characterized by several anchoring threads, which with the one end thereof are fastened to the stent, and also with a brace fastening the anchoring threads with the other end thereof to the distal chamber wall to provide tension between the heart chamber wall and the proximally anchored anchoring elements. | 11-08-2012 |
20130184811 | Device and Method for Replacing Mitral Valve - A prosthetic mitral valve assembly and method of inserting the same is disclosed. In certain disclosed embodiments, the prosthetic mitral valve assembly has a flared upper end and a tapered portion to fit the contours of the native mitral valve. The prosthetic mitral valve assembly can include a stent or outer support frame with a valve mounted therein. The assembly can be adapted to expand radially outwardly and into contact with the native tissue to create a pressure fit. One embodiment of a method includes positioning the mitral valve assembly below the annulus such that the annulus itself can restrict the assembly from moving in an upward direction towards the left atrium. The mitral valve assembly is also positioned so that the leaflets of the mitral valve hold the assembly to prevent downward movement of the assembly towards the left ventricle. | 07-18-2013 |
20130190861 | Prosthetic Valve for Replacing Mitral Valve - Embodiments of prosthetic valves for implantation within a native mitral valve are provided. A preferred embodiment of a prosthetic valve includes a radially compressible main body and a one-way valve portion. The prosthetic valve further comprises at least one ventricular anchor coupled to the main body and disposed outside of the main body. A space is provided between an outer surface of the main body and the ventricular anchor for receiving a native mitral valve leaflet. The prosthetic valve preferably includes an atrial sealing member adapted for placement above the annulus of the mitral valve. Methods and devices for delivering and implanting the prosthetic valve are also described. | 07-25-2013 |
20140214159 | PROSTHETIC VALVES AND RELATED INVENTIONS - This invention relates to the design and function of a compressible valve replacement prosthesis, collared or uncollared, which can be deployed into a beating heart without extracorporeal circulation using a transcatheter delivery system. The design as discussed focuses on the deployment of a device via a minimally invasive fashion and by way of example considers a minimally invasive surgical procedure preferably utilizing the intercostal or subxyphoid space for valve introduction. In order to accomplish this, the valve is formed in such a manner that it can be compressed to fit within a delivery system and secondarily ejected from the delivery system into the annulus of a target valve such as a mitral valve or tricuspid valve. | 07-31-2014 |
20140364944 | TRUNCATED CONE HEART VALVE STENT - A heart valve stent having a section with a heart valve implant and several proximally disposed tissue anchors, also comprising a plurality of anchoring threats, each with a proximate end fastened to the stent or valve and a distal end attached to tissue within a heart chamber to provide tension between the heart chamber tissue and the stent. | 12-11-2014 |
20150196393 | DELIVERY SYSTEMS AND METHODS FOR TRANSCATHETER PROSTHETIC VALVES - This invention relates to a delivery apparatus and method for deployment of a mitral valve replacement. | 07-16-2015 |
20150202044 | PROSTHETIC VALVE FOR REPLACING MITRAL VALVE - Embodiments of prosthetic valves for implantation within a native mitral valve are provided. A preferred embodiment of a prosthetic valve includes a radially compressible main body and a one-way valve portion. The prosthetic valve further comprises at least one ventricular anchor coupled to the main body and disposed outside of the main body. A space is provided between an outer surface of the main body and the ventricular anchor for receiving a native mitral valve leaflet. The prosthetic valve preferably includes an atrial sealing member adapted for placement above the annulus of the mitral valve. Methods and devices for delivering and implanting the prosthetic valve are also described. | 07-23-2015 |
20150305868 | TRUNCATED CONE HEART VALVE STENT - A heart valve stent having a section with a heart valve implant and several proximally disposed tissue anchors, also comprising a plurality of anchoring threats, each with a proximate end fastened to the stent or valve and a distal end attached to tissue within a heart chamber to provide tension between the heart chamber tissue and the stent. | 10-29-2015 |
Patent application number | Description | Published |
20090075445 | Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress - A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si | 03-19-2009 |
20090085097 | METHODS OF FORMING NITRIDE STRESSING LAYER FOR REPLACEMENT METAL GATE AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include removing residual dielectric material from a metal gate structure, and then forming a stress relief layer on a top surface and on a sidewall region of the metal gate structure. A stress is introduced into a channel region disposed beneath the metal gate structure. | 04-02-2009 |
20090230480 | Epitaxial silicon germanium for reduced contact resistance in field-effect transistors - A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed. | 09-17-2009 |
20090315120 | RAISED FACET- AND NON-FACET 3D SOURCE/DRAIN CONTACTS IN MOSFETS - An apparatus comprising a semiconductor substrate; a conductively doped source or drain (source/drain) region at the surface of the substrate; a raised semiconductor layer deposited over the source/drain region to form a raised source/drain region; a via formed in the raised source/drain region having substantially vertical sidewalls reaching partly or substantially to the source/drain region; and a metal contact filling the via. | 12-24-2009 |
20100025775 | Replacement spacers for mosfet fringe capacatance reduction and processes of making same - A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact. | 02-04-2010 |
20100109046 | Methods of forming low interface resistance contacts and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide. | 05-06-2010 |
20110147840 | WRAP-AROUND CONTACTS FOR FINFET AND TRI-GATE DEVICES - A semiconductor device comprises a substrate and a semiconductor body formed on the substrate. The semiconductor body comprises a source region; and a drain region. The source region or the drain region, or combinations thereof, comprises a first side surface, a second side surface, and a top surface. The first side surface is opposite the second side surface, the top surface is opposite the bottom surface. The source region or the drain region, or combinations thereof, comprise a metal layer formed on the substantially all of the first side surface, substantially all of the second side surface, and the top surface. | 06-23-2011 |
Patent application number | Description | Published |
20110079861 | Advanced Transistors with Threshold Voltage Set Dopant Structures - An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5×10 | 04-07-2011 |
20110121404 | ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION - An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10 | 05-26-2011 |
20110248352 | LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICATION THEREOF - A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 10-13-2011 |
20110309447 | TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATION THEREOF - A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 12-22-2011 |
20110309450 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATION THEREOF WITH MIXED METAL TYPES - A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device. | 12-22-2011 |
20120083080 | METHOD FOR REDUCING PUNCH-THROUGH IN A TRANSISTOR DEVICE - Punch-through in a transistor device is reduced by forming a well layer in an implant region, forming a stop layer in the well layer of lesser depth than the well layer, and forming a doped layer in the stop layer of lesser depth than the stop layer. The stop layer has a lower concentration of impurities than the doped layer in order to prevent punch-through without increasing junction leakage. | 04-05-2012 |
20120083103 | METHOD FOR MINIMIZING DEFECTS IN A SEMICONDUCTOR SUBSTRATE DUE TO ION IMPLANTATION - Defects in a semiconductor substrate due to ion implantation are minimized by forming an implant region in the semiconductor substrate and subjecting the semiconductor substrate to a first anneal to recrystallize the semiconductor substrate. The semiconductor substrate is subjected to a second anneal to suppress diffusion of implanted ions in the semiconductor substrate. The first anneal being at a lower temperature and longer duration than the second anneal. | 04-05-2012 |
20120139051 | SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS - A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 | 06-07-2012 |
20120223389 | SEMICONDUCTOR STRUCTURE WITH IMPROVED CHANNEL STACK AND METHOD FOR FABRICATION THEREOF - A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer. | 09-06-2012 |
20130161743 | SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS - A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 | 06-27-2013 |
20130181298 | ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION - An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10 | 07-18-2013 |
20130328129 | LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICATION THEREOF - A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 12-12-2013 |
20140001571 | SEMICONDUCTOR STRUCTURE WITH MULTIPLE TRANSISTORS HAVING VARIOUS THRESHOLD VOLTAGES AND METHOD OF FABRICATION THEREOF | 01-02-2014 |
20140015067 | SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS - A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 | 01-16-2014 |
20140035060 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATION THEREOF WITH MIXED METAL TYPES - A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device. | 02-06-2014 |
20140084385 | DEEPLY DEPLETED MOS TRANSISTORS HAVING A SCREENING LAYER AND METHODS THEREOF - A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure. | 03-27-2014 |
20140103406 | SEMICONDUCTOR STRUCTURE WITH REDUCED JUNCTION LEAKAGE AND METHOD OF FABRICATION THEREOF - A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation. | 04-17-2014 |
20140119099 | DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS, AND RELATED METHODS - A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region. | 05-01-2014 |
20140167156 | ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION - An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10 | 06-19-2014 |
20140167157 | SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS - A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 | 06-19-2014 |
20140248753 | ANALOG TRANSISTOR - An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants. The channel is supported on a screen layer doped to have an average dopant density at least five times as great as the average dopant density of the substantially undoped channel which, in turn, is supported by a doped well having an average dopant density at least twice the average dopant density of the substantially undoped | 09-04-2014 |
20140284722 | TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATION THEREOF - A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 09-25-2014 |
20150061012 | HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES - A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control. | 03-05-2015 |
20150333144 | High Uniformity Screen and Epitaxial Layers for CMOS Devices - A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control. | 11-19-2015 |
20150340460 | ADVANCED TRANSISTORS WITH THRESHOLD VOLTAGE SET DOPANT STRUCTURES - An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5×10 | 11-26-2015 |
Patent application number | Description | Published |
20140238258 | Colored Pyrotechnic Smoke-Producing Composition - A colored pyrotechnic smoke-producing composition has an oxidizer, a fuel, a flame retardant, a dye, a coolant, and a binder. The oxidizer may be potassium chlorate. The fuel may be starch, dextrose, lactose, and/or sucrose. The coolant may be sodium bicarbonate or magnesium carbonate. The binder may be nitrocellulose or a halogen-free thermoplastic. The flame retardant may be one or more nitrogen-rich compounds. The composition may be in pelletized form or in the form of a solid charge. The composition may consist of on a mass basis oxidizer 20-35%, fuel 15-25%, flame retardant 5-15%, dye 27-40%, coolant 8-18%, and binder 1-2%. The invention may be a device consisting of a body filled with the composition and a first fire starter composition, and an attached squib igniter. The body may be a grenade. A process for producing the composition is also disclosed. | 08-28-2014 |
20150239793 | Flameless Igniting Slurry Composition and Method of Preparing - A flameless igniting slurry composition has an oxidizer, a fuel, a flame retardant, a liquid, and a rheology modifier. The rheology modifier and the flame retardant may be in particulate form. The flame retardant may be a water-soluble salt. The liquid may be water. The oxidizer may be potassium nitrate. The fuel may be silicon and charcoal. The composition may consist of on a mass basis 25-50% oxidizer, 20-30% fuel, 2-5% flame retardant, and 0.5-10% rheology modifier. The invention may be a device consisting of a shape of absorbent web material impregnated with the composition in a dried state. The invention may be a device consisting of the composition in a dried, particulate form. A process for producing the composition is also disclosed. | 08-27-2015 |
Patent application number | Description | Published |
20090117888 | WIRELESS DEVICE HAVING CONFIGURABLE MODES - A wireless device having user defined configurable modes includes a memory have at least one configuration segment containing configuration information relating to at least one application or mode. The user enters the user defined configuration that causes a control processor to configure the wireless device based on the configuration information. | 05-07-2009 |
20090119468 | SYSTEMS, METHODS, AND APPARATUSES FOR ERASING MEMORY ON WIRELESS DEVICES - A wireless device having a memory is provided. The memory or a protected portion of the memory is subject to a hard erasure of the memory vs. a soft erasure of the memory if a plurality of sensors indicate a threat to the device exists. The threat may be detected by a plurality of sensors, such as, a timer, a connectivity sensor, a location sensor or geo-fence, a breech sensor, an authentication procedure or the like. | 05-07-2009 |
20090156199 | MONITORING AND TROUBLESHOOTING A MODULE ASSOCIATED WITH A PORTABLE COMMUNICATION DEVICE - Methods, apparatuses, and software to monitor, troubleshoot, or diagnose one or more specialty modules associated with a portable communication device are provided. The methods, apparatuses, and software identify the specialty module, obtain and execute procedures to monitor, test, or diagnose the specialty module. If unsatisfactory, error, defective or the like performance is identified, a solution is applied to correct, the performance. | 06-18-2009 |