| Patent application number | Description | Published |
|---|
| 20080314565 | METHOD AND APPARATUS FOR CHIP COOLING - In one embodiment, the invention is a method and apparatus for chip cooling. One embodiment of a system for cooling a heat-generating device, such as a semiconductor chip, includes a vaporization chamber for at least partially vaporizing a stream of liquid in a stream of a gas to produce a mixture of gas, vapor and liquid and a heat sink coupled to the vaporization chamber for transferring heat from the heat-generating device to the mixture. | 12-25-2008 |
| 20090179279 | METAL GATE ELECTRODE STABILIZATION BY ALLOYING - Stabilized metal gate electrode for complementary metal-oxide-semiconductor (“CMOS”) applications and methods of making the stabilized metal gate electrodes are disclosed. Specifically, the metal gate electrodes are stabilized by alloying wherein the alloy comprises a metal selected from the group consisting of Re, Ru, Pt, Rh, Ni, Al and combinations thereof and an element selected from the group consisting of W, V, Ti, Ta and combinations thereof. | 07-16-2009 |
| 20090294106 | METHOD AND APPARATUS FOR CHIP COOLING - In one embodiment, the invention is a method and apparatus for chip cooling. One embodiment of an apparatus for cooling a heat-generating device includes an inlet for receiving a fluid, a manifold comprising a plurality of apertures formed therein for decreasing the pressure of the fluid from a first pressure by adiabatic expansion for impinging the fluid on the heat-generating device once the pressure of the fluid is decreased from the first pressure. | 12-03-2009 |
| 20090294989 | FORMATION OF VERTICAL DEVICES BY ELECTROPLATING - The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures. | 12-03-2009 |
| 20090301890 | FORMATION OF NANOSTRUCTURES COMPRISING COMPOSITIONALLY MODULATED FERROMAGNETIC LAYERS BY PULSED ECD - The present invention is related to a method for forming a structure that contains alternating first and second ferromagnetic layers of different material compositions. A substrate containing a supporting matrix with at least one open pore and a conductive base layer is first formed. Electroplating of the substrate is then carried out in an electroplating solution that contains at least one ferromagnetic metal element and one or more additional, different metal elements. A pulsed current with alternating high and low potentials is applied to the conductive base layer of the substrate structure to thereby form alternating ferromagnetic layers of different material compositions in the open pore of the supporting matrix. | 12-10-2009 |
| 20090302305 | SELF-CONSTRAINED ANISOTROPIC GERMANIUM NANOSTRUCTURE FROM ELECTROPLATING - A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation. | 12-10-2009 |
| 20090302353 | STRUCTURES CONTAINING ELECTRODEPOSITED GERMANIUM AND METHODS FOR THEIR FABRICATION - Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits. | 12-10-2009 |
| 20110012085 | METHODS OF MANUFACTURE OF VERTICAL NANOWIRE FET DEVICES - A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom electrode. Fill the columnar pore by plating a vertical semiconductor nanowire having a bottom end contacting the bottom electrode. The semiconductor nanowire forms an FET device with a FET channel region between a source region and a drain region formed in distal ends of the vertical semiconductor nanowire. Form a gate dielectric layer around the channel region of the vertical semiconductor nanowire and then form a gate electrode around the gate dielectric layer. Form a top electrode contacting a top end of the vertical semiconductor nanowire. | 01-20-2011 |
| 20110108803 | VERTICAL NANOWIRE FET DEVICES - A Vertical Field Effect Transistor (VFET) formed on a substrate, with a conductive bottom electrode formed thereon. A bottom dielectric spacer layer and a gate dielectric layer surrounded by a gate electrode are formed thereabove. Thereabove is an upper spacer layer. A pore extends therethrough between the electrodes. A columnar Vertical Semiconductor Nanowire (VSN) fills the pore and between the top and bottom electrodes. An FET channel is formed in a central region of the VSN between doped source and drain regions at opposite ends of the VSN. The gate dielectric structure, that is formed on an exterior surface of the VSN above the bottom dielectric spacer layer, separates the VSN from the gate electrode. | 05-12-2011 |
