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Luan, CA
Andy Luan, Palo Alto, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110240105 | LEAKAGE PATHWAY LAYER FOR SOLAR CELL - Leakage pathway layers for solar cells and methods of forming leakage pathway layers for solar cells are described. | 10-06-2011 |
Chenggang Luan, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110197208 | METHOD AND APPARATUS FOR REACHING SMALL MARKETS WITH A CULTURE SPECIFIC ON-LINE COMMERCE SERVICE - A method is described that comprises providing a cultural specific on-line commerce experience for an end user by translating an action of the end user into a standard format used by an on-line auctioneer and by causing the translated action to be sent over a network. The action is taken through a cultural specific end user interface. | 08-11-2011 |
Chung Chen Luan, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100008378 | Ethernet Controller Implementing a Performance and Responsiveness Driven Interrupt Scheme - A method of generating frame receive interrupts in an Ethernet controller including receiving incoming data frames and storing data frames into a receive queue, monitoring the number of received data frames, and when the number of received data frames exceeds a first threshold, generating a frame receive interrupt. In another embodiment, the method further includes monitoring the amount of received data stored in the receive queue and generating a frame receive interrupt when the first threshold is exceeded and when the amount of received data stored in the receive queue exceeds a second threshold. In yet another embodiment, the method further includes monitoring the time duration of the data frames stored in the receive queue, and generating a frame receive interrupt when the number of received data frames exceeds the first threshold or when the time duration of the data frames stored in the receive queue exceeds a third threshold. | 01-14-2010 |
| 20100011140 | Ethernet Controller Using Same Host Bus Timing for All Data Object Access - An Ethernet controller has a host interface for coupling to a host processor and a physical layer transceiver for coupling to a data network and includes multiple data objects having different access times where the data objects communicate with the host interface over an internal data bus. The Ethernet controller includes a data object interface module coupled between the host interface and the internal data bus where the data object interface module has a first access time for handling data requests for the data objects received on the host interface from the host processor, and a control logic circuit coupled to control the operation of the data object interface module. Data requests from the host processor for accessing data stored in the multiple data objects are carried out through the data object interface module using the first access time, regardless of the different access times of the multiple data objects. | 01-14-2010 |
| 20100020809 | True Ring Networks Using Tag VLAN Filtering - A method in a network device configured in a true ring network where the network device has a first port and a second port connected to the true ring network and a third port connected to a processor including: connecting the network device to transmit data packets in a single direction around the true ring network including an ingress port and an egress port; enabling ingress tag VLAN filtering on the ingress port only; configuring a VLAN table in the network device to terminate an incoming data packet when a VID tag (VLAN identifier tag) of the incoming data packet matches the local VID tag of the network device; and configuring the VLAN table in the network device to accept the incoming data packet when the VID tag of the incoming data packet does not match the local VID tag of the network device. | 01-28-2010 |
| 20100202470 | Dynamic Queue Memory Allocation With Flow Control - A method in an Ethernet controller for allocating memory space in a buffer memory between a transmit queue (TXQ) and a receive queue (RXQ) includes allocating initial memory space in the buffer memory to the RXQ and the TXQ; defining a RXQ high watermark and a RXQ low watermark; receiving an ingress data frame; determining if a memory usage in the RXQ exceeds the RXQ high watermark; if the RXQ high watermark is not exceeded, storing the ingress data frame in the RXQ; if the RXQ high watermark is exceeded, determining if there are unused memory space in the TXQ; if there are no unused memory space in the TXQ, transmitting a pause frame to halt further ingress data frame; if there are unused memory space in the TXQ, allocating unused memory space in the TXQ to the RXQ; and storing the ingress data frame in the RXQ. | 08-12-2010 |
Harry S. Luan, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090085127 | NON-VOLATILE SEMICONDUCTOR MEMORY BASED ON ENHANCED GATE OXIDE BREAKDOWN - A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming results. The conductivity of the programmed memory cell is increased greatly and conductivity variation between the memory cells is reduced. This is achieved by adding a body bias during the programming process. The body here refers to a P-well formed within the deep N-Well. Furthermore, the read voltage offset is reduced greatly with this new memory configuration. These improved programming results will allow faster read speed and lower read voltage. This new structure also reduces current leakage from a memory array during programming. | 04-02-2009 |
| 20100054048 | METHOD AND APPARATUS FOR PROGRAMMING AUTO SHUT-OFF - A method and system for enabling auto shut-off of programming of a non-volatile memory cell is disclosed. The system includes a memory array having a plurality of memory cells, each cell storing one bit of data. During the programming process, programming signals are applied to the target memory cells. A predefined period of time after the programming signals are applied, the auto shut-off system begins sensing an output signal from the memory cell. After the system detects an output signal from the memory cell, the system waits for a second predefined period of time before turning off the programming voltages. The system may be configured to sense an output voltage from the memory cell. The system then compares the output voltage to a reference voltage in order to detect when the cell is programmed. Alternatively, the system may sense an output current from the memory cell. The system then compares the output current to a reference current to detect when the cell is programmed. | 03-04-2010 |
Harry Shengwen Luan, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090080275 | REDUCING BIT LINE LEAKAGE CURRENT IN NON-VOLATILE MEMORIES - In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations. | 03-26-2009 |
Hsin-Chiao Luan, Palo Alto, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080230372 | Deposition system with electrically isolated pallet and anode assemblies - A system for substrate deposition. The system includes a wafer pallet and an anode. The wafer pallet has a bottom and a top. The top of the wafer pallet is configured to hold a substrate wafer. The anode has a substantially fixed position relative to the wafer pallet and is configured to move with the wafer pallet through the deposition chamber. The anode is electrically isolated from the substrate wafer. | 09-25-2008 |
| 20080283490 | PROTECTION LAYER FOR FABRICATING A SOLAR CELL - A method for fabricating a solar cell is described. The method includes first providing, in a process chamber, a substrate having a light-receiving surface. An anti-reflective coating (ARC) layer is then formed, in the process chamber, above the light-receiving surface of the substrate. Finally, without removing the substrate from the process chamber, a protection layer is formed above the ARC layer. | 11-20-2008 |
| 20090022572 | Cluster tool with a linear source - Systems and methods combining a cluster chamber with linear sources are described. A plurality of wafers is mounted on a pallet. A central robot in a cluster chamber moves the pallet among chambers connected to the cluster chamber chamber. At least one of the chambers connected to the cluster chamber includes a linear deposition source, the pallet moveable relative to the linear deposition source. | 01-22-2009 |
| 20090151784 | Anti-Reflective Coating With High Optical Absorption Layer For Backside Contact Solar Cells - A multilayer anti-reflection structure for a backside contact solar cell. The anti-reflection structure may be formed on a front side of the backside contact solar cell. The anti-reflection structure may include a passivation level, a high optical absorption layer over the passivation level, and a low optical absorption layer over the high optical absorption layer. The passivation level may include silicon dioxide thermally-grown on a textured surface of the solar cell substrate, which may be an N-type silicon substrate. The high optical absorption layer may be configured to block at least 10% of UV radiation coming into the substrate. The high optical absorption layer may comprise high-k silicon nitride and the low optical absorption layer may comprise low-k silicon nitride. | 06-18-2009 |
| 20100071765 | METHOD FOR FABRICATING A SOLAR CELL USING A DIRECT-PATTERN PIN-HOLE-FREE MASKING LAYER - A method for fabricating a solar cell is described. The method includes first providing a substrate having a dielectric layer disposed thereon. A pin-hole-free masking layer is then formed above the dielectric layer. Finally, without the use of a mask, the pin-hole-free masking layer is patterned to form a patterned pin-hole-free masking layer. | 03-25-2010 |
| 20100129955 | PROTECTION LAYER FOR FABRICATING A SOLAR CELL - A method for fabricating a solar cell is described. The method includes first providing, in a process chamber, a substrate having a light-receiving surface. An anti-reflective coating (ARC) layer is then formed, in the process chamber, above the light-receiving surface of the substrate. Finally, without removing the substrate from the process chamber, a protection layer is formed above the ARC layer. | 05-27-2010 |
Leo Shyh-Wei Luan, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090213487 | EFFICIENT METHOD TO DETECT DISK WRITE ERRORS - A write error detection mechanism for a computer data disk drive or storage controller writes and then verifies data to detect disk write errors. It allows the heads to be moved to other tracks to do other jobs in the time it takes the disk to rotate from the point the data was written and to return there again so it can be read to verify the write. The data written is temporarily stored in feature table memory outside the disk, so it can be used as in the comparison later when the written data can be read for the verify. In the interim, other write-and-verify and read operations can be pipelined, or multitasked using the same head, even on different tracks. | 08-27-2009 |
| 20100205156 | Remote Access Agent for Caching in a SAN File System - A system and method is disclosed for maintaining, in a Storage Area Network (SAN), the consistency of a local copy of a remote file system sub-tree obtained from a remote source. Directory structure of the remote file system sub-tree is mapped to a remote container attached to the SAN and each remote object of the remote file system sub-tree is represented as a local object component of the remote container. Next, each of the local objects are labeled with attributes associated with the represented remote object, and metadata describing each of the local objects is stored in a metadata server. Also, a consistency policy is associated with each of the local objects in the remote container (wherein the policy defines conditions for checking freshness of said labeled attributes), and the local object components of remote container is updated in accordance with the consistency policy. | 08-12-2010 |
Peng Luan, South San Francisco, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110129480 | ANTI-FERROPORTIN 1 MONOCLONAL ANTIBODIES AND USES THEREOF - Provided are monoclonal antibodies and antigen-binding fragments thereof that bind to, and inhibit the activity of human FPN1, and which are effective in maintaining or increasing the transport of iron out of mammalian cells and/or maintaining or increasing the level of serum iron, reticulocyte count, red blood cell count, hemoglobin, and/or hematocrit in a subject in vivo. | 06-02-2011 |
Peng Luan, Redwood City, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080241233 | TARGETED DELIVERY AND EXPRESSION OF PROCOAGULANT HEMOSTATIC ACTIVITY - A platelet substitute consisting of large unilamellar lipid vesicles that contain phosphatidylserine or another procoagulant (clot-promoting) phospholipid, a protein that has binding affinity for collagen or other component of the vessel wall that becomes exposed upon vessel injury, and/or a phospholipid scramblase, has been developed. This platelet substitute provides a means for selectively delivering procoagulant phospholipids and/or fatty acids to the site of vessel injury through targeted adherence to collagen or other component exposed upon vessel injury. These are particularly effective due to the combination of targeting procoagulant vesicles to a site of injury, and triggered exposure of phosphatidylserine (PS) on the surface. | 10-02-2008 |
Peng Luan, Livermore, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110027261 | ANTI-HEPCIDIN ANTIBODIES AND USES THEREOF - Monoclonal antibodies are provided that selectively bind human hepcidin-25 and are characterized as having high affinity for human hepcidin-25 and strong human mature hepcidin neutralizing properties. The antibodies of the invention are useful therapeutically for increasing serum iron levels, reticulocyte count, red blood cell count, hemoglobin, and/or hematocrit in a human and for the treatment and diagnosis of mature hepcidin-promoted disorders such as anemia, in a human subject. | 02-03-2011 |
Sheng Luan, Berkeley, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110059859 | Molecule Detecting System - The invention disclosed here has several key elements: direct probe-on-sensor detection, mesh probe, and mesh reporter. Furthermore, the mesh probe and reporter shall have some physical cross-linking between the polymer backbone(s), either covalently or non-covalently. In combination, this invention enables one to build an ultra-sensitive, low-cost, and highly portable system for molecular detection. Among its many potential applications is a direct detection of nucleic acids in crude lysate in a multiplex format, without the requirements for nucleic acids extraction and amplification. Such an improvement is likely to change the practice of genotyping and gene expression profiling done in a clinic setting. Another application is an ultrasensitive ELIZA assay in a multiplex format. | 03-10-2011 |
Shyi-Perng Phillip Luan, Walnut Creek, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110197431 | Manufacturing Methods for a Triple Layer Winding Pattern - A method of manufacturing a triple-winding layer arrangement for a three-phase, four pole motor is provided. | 08-18-2011 |
| 20110198960 | Dual Layer Winding Pattern and Methods of Manufacturing Same - A dual-winding layer arrangement for a three-phase, four pole motor is provided as well as a method of manufacturing the same. | 08-18-2011 |
| 20110198961 | Triple Layer Winding Pattern and Methods of Manufacturing Same - A triple-winding layer arrangement for a three-phase, four pole motor is provided as well as a method of manufacturing the same. | 08-18-2011 |
| 20110198963 | Dual Layer Winding Pattern - A dual-winding layer arrangement for a three-phase, four pole motor is provided. | 08-18-2011 |