| Patent application number | Description | Published |
|---|
| 20090087987 | METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING IMPROVED CONTACTS - A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This embodiment of the device includes an underlayer of material having an opening therein; a layer of thin conductive material formed on the underlayer and in the opening; and overlayer of material having a contact hole therethrough formed on the layer of thin conductive material; a conductor contacting the layer of thin conductive material through the contact hole; and wherein the opening in the underlayer is positioned below the contact hole and sized and shaped to form a localized thick region in the layer of thin conductive material within the opening. | 04-02-2009 |
| 20090242961 | RECESSED CHANNEL SELECT GATE FOR A MEMORY DEVICE - A memory device comprising one or more recessed channel select gates and at least one charge trapping layer. | 10-01-2009 |
| 20100092891 | PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES - Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer. | 04-15-2010 |
| 20100203727 | METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION - Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate. | 08-12-2010 |
| 20100210111 | PITCH REDUCED PATTERNS RELATIVE TOPHOTOLITHOGRAPHY FEATURES - Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate. | 08-19-2010 |
