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Lu, OR
Jasmine Lu, Canby, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20090045830 | AUTOMATED CONTACT ALIGNMENT TOOL - A method for determining the alignment of a plurality of contacts in an electronic testing machine is disclosed. The contacts are swept over an electronic component taking a plurality of electrical readings. These electrical readings are charted against a desired orientation to determine alignment. Alignment can be corrected as necessary using an adjustment mechanism. | 02-19-2009 |
Mengcheng Lu, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20110147831 | METHOD FOR REPLACEMENT METAL GATE FILL - An exemplary embodiment of a method for forming a gate for a planar-type or a finFET-type transistor comprises forming a gate trench that includes an interior surface. A first work-function metal is formed on the interior surface of the gate trench, and a low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. Another exemplary embodiment provides that a second work-function metal is formed on the first work-function metal, and then the low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. | 06-23-2011 |
Shih-Lien Lu, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20090172243 | Providing metadata in a translation lookaside buffer (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed. | 07-02-2009 |
| 20090328057 | SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX - A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied. | 12-31-2009 |
| 20100146368 | PERFORMING MULTI-BIT ERROR CORRECTION ON A CACHE LINE - A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits. | 06-10-2010 |
Shih-Lien L. Lu, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20080307277 | DELAY FAULT DETECTION USING LATCH WITH ERROR SAMPLING - Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value. | 12-11-2008 |
| 20100052730 | METHOD AND APPARATUS FOR LATE TIMING TRANSITION DETECTION - Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed. | 03-04-2010 |
| 20110161783 | METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ERROR CORRECTING CODES (ECC) - An apparatus and method is described herein directly matching coded tags. An incoming tag address is encoded with error correction codes (ECCs) to obtain a coded, incoming tag. The coded, incoming tag is directly compared to a stored, coded tag; this comparison result, in one example, yields an m-bit difference between the coded, incoming tag and the stored, coded tag. ECC, in one described embodiment, is able to correct k-bits and detect k+1 bits. As a result, if the m-bit difference is within 2k+2 bits, then valid codes—coded tags—are detected. As an example, if the m-bit difference is less than a hit threshold, such as k-bits, then a hit is determined, while if the m-bit difference is greater than a miss threshold, such as k+1 bits, then a miss is determined. | 06-30-2011 |
Shlh-Lian L. Lu, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20100079184 | Sequential circuit with error detection - Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch. | 04-01-2010 |
Victor Lu, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20090292592 | METHOD AND APPARATUS FOR REAL-TIME REPORTING OF ELECTRONIC COMMERCE ACTIVITY - A method and apparatus is disclosed for tracking and reporting electronic commerce activity over a web site that is stored on a first server coupled to a wide area network. The web page is programmed to include data fields reflecting commerce transaction activity and data mining code. The web page is uploaded to a visitor computer responsive to a request over the wide area network from the visitor computer. Commerce information is accepted within the data fields of the web page at the visitor computer to form a completed web page. The data mining code is operated on the visitor computer to obtain technical and commercial data and sent to a second server on the wide area network for logging and analysis. | 11-26-2009 |
| 20090293001 | SYSTEM AND METHOD FOR GENERATING AND REPORTING COOKIE VALUES AT A CLIENT NODE - A method and apparatus for tracking and reporting traffic activity on a web site whereby cookie data is compiled at the visitor computer using cookie processing script embedded within the web page downloaded over the Internet and operable on the visitor computer. Data mining code within the downloaded web page is operable on the visitor computer to obtain web browsing data. The cookie processing script operates in consideration of this web browsing data and an old cookie previously stored on the visitor computer and associated with the visited web page to obtain new cookie values. These new cookie values are then stored on the visitor computer and also attached to an image request sent to a data collection server where they are processed and posted for viewing by the web page owner. As cookie processing and writing occurs completely within the visitor computer, cookie-blocking technologies are circumvented. | 11-26-2009 |
Wilson Lu, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20100078418 | METHOD OF LASER MICRO-MACHINING STAINLESS STEEL WITH HIGH COSMETIC QUALITY - A process to laser micro-machine a metal part with a high cosmetic quality surface includes applying a protective coating layer to at least one surface of the part before micro-machining the part with a laser. The protective coating applied to the high quality cosmetic surface can have a thickness of between about 5 mil and about 10 mil, inclusive and have sufficient adhesion strength to adhere to the part without delaminating during processing. The protective coating applied to the machining surface of the part can be a metallic material, such as a metallic foil or tape. | 04-01-2010 |