Patent application number | Description | Published |
20090172243 | Providing metadata in a translation lookaside buffer (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed. | 07-02-2009 |
20090328057 | SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX - A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied. | 12-31-2009 |
20100146368 | PERFORMING MULTI-BIT ERROR CORRECTION ON A CACHE LINE - A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits. | 06-10-2010 |
20110208944 | Providing Metadata In A Translation Lookaside Buffer (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed. | 08-25-2011 |
20110289380 | METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE - A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state. | 11-24-2011 |
20120079342 | Error Correcting Code Logic for Processor Caches That Uses a Common Set of Check Bits - A processor or other apparatus of an aspect may include a first cache, a first error correction code (ECC) logic for the first cache, a second cache, and a second ECC logic for the second cache. The apparatus may also include an interconnect coupled with or between the first cache and the second cache. The interconnect is operable to transmit data and also check bits corresponding to the data between the first cache and the second cache. A method of an aspect may include accessing data, and check bits corresponding to the data, from a first cache. The data and the check bits may be transmitted over an interconnect from the first cache to a second cache. The data and the check bits may be stored in the second cache. Other methods, apparatus, and systems are also disclosed. | 03-29-2012 |
20120297161 | Providing Metadata In A Translation Lookaside Buffer (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed. | 11-22-2012 |
20140037042 | INTEGRATED NON-VOLATILE MONOTONIC COUNTERS - Some embodiments include a counter having a first generator to generate signals having different frequencies, and a second generator to generate counter values of the counter. Each of the counter values may be based at least in part on a number of transitions of a respective signal among the signals. Other embodiments are described. | 02-06-2014 |
20140095799 | DIFFERENTIATING CACHE RELIABILITY TO REDUCE MINIMUM ON-DIE VOLTAGE - Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions. | 04-03-2014 |
20140337600 | PROVIDING METADATA IN A TRANSLATION LOOKASIDE BUFFER (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed. | 11-13-2014 |
20150085589 | DATA MOVEMENT IN MEMORY DEVICES - Apparatus, systems, and methods for data movement in a memory device are described. In one embodiment, a memory controller comprises logic to move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface. Other embodiments are also disclosed and claimed. | 03-26-2015 |
Patent application number | Description | Published |
20080307277 | DELAY FAULT DETECTION USING LATCH WITH ERROR SAMPLING - Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value. | 12-11-2008 |
20100052730 | METHOD AND APPARATUS FOR LATE TIMING TRANSITION DETECTION - Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed. | 03-04-2010 |
20110161783 | METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ERROR CORRECTING CODES (ECC) - An apparatus and method is described herein directly matching coded tags. An incoming tag address is encoded with error correction codes (ECCs) to obtain a coded, incoming tag. The coded, incoming tag is directly compared to a stored, coded tag; this comparison result, in one example, yields an m-bit difference between the coded, incoming tag and the stored, coded tag. ECC, in one described embodiment, is able to correct k-bits and detect k+1 bits. As a result, if the m-bit difference is within 2k+2 bits, then valid codes—coded tags—are detected. As an example, if the m-bit difference is less than a hit threshold, such as k-bits, then a hit is determined, while if the m-bit difference is greater than a miss threshold, such as k+1 bits, then a miss is determined. | 06-30-2011 |
20120159283 | LOW OVERHEAD ERROR CORRECTING CODE PROTECTION FOR STORED INFORMATION - Embodiments of an invention for low overhead error-correcting-code protection for stored information are described are disclosed. In one embodiment, an apparatus includes a data storage structure, a first check value storage structure, a second check value storage structure, and check value generation hardware. The data storage structure is to store a plurality of first data values. The first check value storage structure is to store a plurality of first check values. The second check value storage structure is to store a plurality of second check values. The check value generation hardware is to generate the first check values and the second check values. The first check values provide a first level of error protection for the first data values and the second check values provide a second level of error protection for a plurality of second data values. Each of the plurality of first data value has a first data width, and each of the plurality of second data values has a second data width, the second data width being greater than the first data width. Each of the second data values is a concatenation of one of the first data values and at least another of the first data values. | 06-21-2012 |
20130262957 | Method Of Correcting Adjacent Errors By Using BCH-Based Error Correction Coding - An apparatus is provided that comprises a processor. The processor comprises a cache to store data, a decoder, an error classification module, and an error correction module. The cache stores data, the data encoded as a codeword. The decoder reads the codeword from cache and calculates a syndrome of the codeword using an H-matrix. The error classification module determines an error type of the syndrome. The H-matrix is redesigned such that the columns form a geometrical sequence, and as a result not only the t-bit random errors but also (t+1) bit adjacent errors can be corrected. The error correction module, triggered by the enhanced error classification module, takes one of two sets of inputs depends on the error type (either random or adjacent error) and produces corrected data from the syndrome when the syndrome comprises a detectable and correctable error. | 10-03-2013 |
20140074902 | NUMBER REPRESENTATION AND MEMORY SYSTEM FOR ARITHMETIC - A method, device and system for representing numbers in a computer including storing a floating-point number M in a computer memory; representing the floating-point number M as an interval with lower and upper bounds A and B when it is accessed by using at least two floating-point numbers in the memory; and then representing M as an interval with lower and upper bounds A and B when it is used in a calculation by using at least three floating-point numbers in the memory. Calculations are performed using the interval and when the data is written back to the memory it may be stored as an interval if the size of the interval is significant, i.e. larger than a first threshold value. A warning regarding the suspect accuracy of any data stored as an interval may be issued if the interval is too large, i.e. larger than a second threshold value. | 03-13-2014 |
20140122947 | Sequential Circuit with Error Detection - Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch. | 05-01-2014 |
20140136820 | Recycling Error Bits in Floating Point Units - A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprising a floating point unit (FPU) to generate a result value from applying an operation on floating point number inputs to the FPU and generate an error value using the result value. The FPU also writes the result value to a first register of the processing device dedicated to storing results from the operation of the FPU and writes the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU. | 05-15-2014 |
20140149822 | SELECTIVE ERROR CORRECTION IN MEMORY TO REDUCE POWER CONSUMPTION - Embodiments of apparatus, methods, systems, and devices are described herein for selective error correction in memory with multiple operation modes. In various embodiments, an error correction block (e.g., of a memory controller) may be configured to perform error correction on data read from a first portion of a memory based on a corresponding error correction code read from a second portion of the memory, and to calculate and store the error correction code. A control block coupled to the error correction block may be configured to selectively enable/disable the error correction block to perform the error correction, and to calculate and store the error correction code, based at least in part on a current operation mode of the memory. | 05-29-2014 |
20140181618 | ERROR DETECTION AND CORRECTION APPARATUS AND METHOD - Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In embodiments, one or more error detection modules may be configured to detect a plurality of error types in the codeword. One or more error correction modules coupled with the one or more error detection modules may be further configured to correct errors of the plurality of error types once they are detected by the one or more error detection modules. Other embodiments may be described and/or claimed. | 06-26-2014 |
20150149714 | CONSTRAINING PREFETCH REQUESTS TO A PROCESSOR SOCKET - In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed. | 05-28-2015 |
Patent application number | Description | Published |
20090292592 | METHOD AND APPARATUS FOR REAL-TIME REPORTING OF ELECTRONIC COMMERCE ACTIVITY - A method and apparatus is disclosed for tracking and reporting electronic commerce activity over a web site that is stored on a first server coupled to a wide area network. The web page is programmed to include data fields reflecting commerce transaction activity and data mining code. The web page is uploaded to a visitor computer responsive to a request over the wide area network from the visitor computer. Commerce information is accepted within the data fields of the web page at the visitor computer to form a completed web page. The data mining code is operated on the visitor computer to obtain technical and commercial data and sent to a second server on the wide area network for logging and analysis. | 11-26-2009 |
20090293001 | SYSTEM AND METHOD FOR GENERATING AND REPORTING COOKIE VALUES AT A CLIENT NODE - A method and apparatus for tracking and reporting traffic activity on a web site whereby cookie data is compiled at the visitor computer using cookie processing script embedded within the web page downloaded over the Internet and operable on the visitor computer. Data mining code within the downloaded web page is operable on the visitor computer to obtain web browsing data. The cookie processing script operates in consideration of this web browsing data and an old cookie previously stored on the visitor computer and associated with the visited web page to obtain new cookie values. These new cookie values are then stored on the visitor computer and also attached to an image request sent to a data collection server where they are processed and posted for viewing by the web page owner. As cookie processing and writing occurs completely within the visitor computer, cookie-blocking technologies are circumvented. | 11-26-2009 |
20110276367 | METHOD AND APPARATUS FOR REAL-TIME REPORTING OF ELECTRONIC COMMERCE ACTIVITY - A method and apparatus is disclosed for tracking and reporting electronic commerce activity over a web site that is stored on a first server coupled to a wide area network. The web page is programmed to include data fields reflecting commerce transaction activity and data mining code. The web page is uploaded to a visitor computer responsive to a request over the wide area network from the visitor computer. Commerce information is accepted within the data fields of the web page at the visitor computer to form a completed web page. The data mining code is operated on the visitor computer to obtain technical and commercial data and sent to a second server on the wide area network for logging and analysis. | 11-10-2011 |
20120297062 | SYSTEM AND METHOD FOR GENERATING AND REPORTING COOKIE VALUES AT A CLIENT NODE - A method and apparatus for tracking and reporting traffic activity on a web site whereby cookie data is compiled at the visitor computer using cookie processing script embedded within the web page downloaded over the Internet and operable on the visitor computer. Data mining code within the downloaded web page is operable on the visitor computer to obtain web browsing data. The cookie processing script operates in consideration of this web browsing data and an old cookie previously stored on the visitor computer and associated with the visited web page to obtain new cookie values. These new cookie values are then stored on the visitor computer and also attached to an image request sent to a data collection server where they are processed and posted for viewing by the web page owner. As cookie processing and writing occurs completely within the visitor computer, cookie-blocking technologies are circumvented. | 11-22-2012 |