| Patent application number | Description | Published |
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| 20100122229 | Apparatus and Method of Preventing Congestive Placement - An apparatus of preventing congestive placement is provided. The apparatus comprises a judging module, a pattern generating module, and a placement module. The judging module judges whether a circuit layout comprises a congestive region according to a judging rule. When a judgment result of the judging module is affirmative, the pattern generating module generates a redistribution pattern with a density distribution of blockages. The density distribution gradually decreases outward. The placement module regards the congestive region as the center redistributes the blockages and electronic cells according to the redistribution pattern. | 05-13-2010 |
| 20100242009 | Method and Apparatus For Preventing Congestive Placement - A congestive placement preventing apparatus, applied in a logic circuit layout having 2 | 09-23-2010 |
| 20100271066 | CIRCUIT PROTECTING APPARATUS AND ASSOCIATED METHOD, AND CIRCUIT PROTECTING LAYER - A circuit protecting apparatus is provided. The circuit protecting apparatus comprises a selecting module, a routing module, a processing module, and a controlling module. The selecting module selects for each of a plurality of a minimum-sized routing region a routing pattern from a plurality of predetermined routing patterns, and generates an input signal. The routing module then generates the routing comprising the selected routing patterns on a to-be-protected region to form a circuit protecting layer. The routing receives the input signal and outputs an output signal. The processing module decodes the output signal into a restored signal a compares the restored signal with the input signal to generate a comparison result, according to which the controlling module selectively fails a chip. | 10-28-2010 |
| 20100281443 | Change Point Finding Method and Apparatus - A change point finding method applied to a logic circuit is provided. The method first defines an indication map and performs a functional equivalent check to judge whether the indication map is correct. When a result is confirmative, the method adds a trap to an RTL HDL of the logic circuit, so that a plurality of comparing points are generated in an APR gate level HDL of the logic circuit. Then the method performs a backward functional equivalent check on the APR gate level HDL of the logic circuit to find a change point according to the comparing points. | 11-04-2010 |
| 20110126166 | Apparatus for Preventing Congestive Placement and Associated Method - A congestive placement preventing apparatus applied to a circuit layout including electrical devices is provided. The congestive placement preventing apparatus includes an analyzing module, a reserving module and a placing module. The analyzing module performs a routing congestion analysis on the circuit layout to generate an analysis result of the circuit layout. The reserving module correspondingly disposes a plurality of blockages in the circuit layout according to the analysis result, so that a first space with the blockages and a second space are formed in the circuit layout. After the placing module places the electrical devices in the second space, the placing module removes the blockages from the first space, and redistributes the electrical devices in the first space and the second space according to a redistribution rule. | 05-26-2011 |
| 20110153303 | Static IR (voltage) drop Analyzing Apparatus and Associated Method - A static voltage drop analyzing apparatus applied to a Multi-Threshold Complementary Metal-Oxide-Semiconductor (MTCMOS) transistor is provided. The static voltage drop analyzing apparatus includes a calculating module, a processing module, and a measuring module. The calculating module calculates a voltage drop tolerance according to the voltage drop characteristic of the MTCMOS transistor. The processing module selects a simulation metal layer corresponding to the voltage drop tolerance from a plurality of candidate simulation metal layers, and adds the simulation metal layer into the MTCMOS transistor. The measuring module measures the voltage drop of the simulation metal layer added into the MTCMOS transistor. The measured voltage drop of the simulation layer added into the MTCMOS is substantially the static voltage drop of the MTCMOS transistor. | 06-23-2011 |
| Patent application number | Description | Published |
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| 20090046231 | DISPLAY PANEL AND FABRICATING METHOD THEREOF - A display panel including a substrate, a first electrode layer, a pixel definition layer, a liquid display medium, a cap layer, and a second electrode layer is provided. The first electrode layer is disposed on the substrate. The pixel definition layer is disposed on the first electrode layer, wherein the pixel definition layer has a plurality of openings arranged in array so as to expose a part of the first electrode layer. The liquid display medium is disposed within the openings. The cap layer is connected to the pixel definition layer and covers the liquid display medium, so as to envelop the liquid display medium in the openings. The second electrode layer is disposed on the cap layer. A method of fabricating the display panel is also provided. Accordingly, the thickness of the display panel is decreased and the process of fabricating the display panel is more easily controlled. | 02-19-2009 |
| 20090185255 | ELECTRO-WETTING DISPLAY PANEL - An electro-wetting display panel including a first substrate, an insulator layer, a second substrate, partitioning structures, and electro-wetting display mediums. The first substrate has a plurality of first electrodes. The insulator layer is disposed on the first substrate to cover the first electrodes. The second substrate located above the first substrate and has a plurality of second electrodes. The partitioning structures are disposed on the insulator layer and each defines a pixel region, respectively. At least one of the partitioning structures has a flow channel surrounding the pixel regions, and the flow channel is connected to one of the pixel regions correspondingly. The electro-wetting display mediums are disposed within the pixel regions and the flow channels. When the electro-wetting display mediums are driven by the electric charge between the first electrodes and the second electrodes, the electro-wetting display mediums move between the pixel regions and the flow channels. | 07-23-2009 |
