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Low, CA
Andrew Low, Ontario CA
| Patent application number | Description | Published |
|---|---|---|
| 20110054879 | Accelerated Execution for Emulated Environments - The illustrative embodiments provide a computer implemented method, apparatus, and computer program product for accelerating execution of a program, written in an object oriented programming language, in an emulated environment. In response to receiving a request for an accelerated communications session from a guest virtual machine in the emulated environment, a native virtual machine is initiated external to the emulated environment but within the computing device hosting the emulated environment. Thereafter, an accelerated communications link is established between the guest virtual machine and the native virtual machine. The accelerated communications link enables a transfer of managed code between the guest virtual machine and the native virtual machine. The managed code is then executed by the native virtual machine. | 03-03-2011 |
Andrew R. Low, Stittsville CA
| Patent application number | Description | Published |
|---|---|---|
| 20110239219 | PROTECTING SHARED RESOURCES USING SHARED MEMORY AND SOCKETS - Shared memory and sockets are used to protect shared resources in an environment where multiple operating systems execute concurrently on the same hardware. Rather than using spinlocks for serializing access to the shared resources, when a thread is unable to acquire a shared resource because that resource is already held by another thread, the thread that was unable to acquire the resource creates a socket with which it will wait to be notified that the shared resource has been released. The sockets may be network sockets or in-memory sockets that are accessible across the multiple operating systems; if sockets are not available in a particular implementation, communication technology that provides analogous services between operating systems may be used instead. In an optional aspect, fault tolerance is provided to address socket failures, in which case one or more threads may fall back (at least temporarily) to using spinlocks. As another option, a locking service may execute on each operating system to provide a programming interface through which threads can invoke operations for holding and releasing the lock. | 09-29-2011 |
| 20110264841 | SHARING OF CLASS DATA AMONG VIRTUAL MACHINE APPLICATIONS RUNNING ON GUESTS IN VIRTUALIZED ENVIRONMENT USING MEMORY MANAGEMENT FACILITY - A method, system and computer program product for sharing class data among virtual machine applications running on one or more guests in a virtualized environment. A control program in a virtual operating system is used to manage the user portions of the virtual operating system, each commonly referred to as a guest. A guest operating system runs on each guest and applications can run on each guest operating system. A memory management facility manages shared memory which includes a class cache configured to store class data. The shared memory may be mounted onto each guest using a cluster file system or accessed via an API interface thereby allowing the class cache to be shared across the guests. By sharing the class cache among the guests, multiple copies of the same class data are no longer necessary thereby optimally using the physical memory on the host. | 10-27-2011 |
Andrew Russell Low, Stittsville CA
| Patent application number | Description | Published |
|---|---|---|
| 20120017204 | STRING CACHE FILE FOR OPTIMIZING MEMORY USAGE IN A JAVA VIRTUAL MACHINE - A method, system and computer program product for optimizing memory usage associated with duplicate string objects in a Java virtual machine. The method comprises scanning a heap of the Java virtual machine at the end of the start-up process of the virtual machine to identify duplicate strings associated with the virtual machine, storing the identified strings in a string cache file, and determining whether a new string that needs to be created during start-up already exists in the string cache file. The duplicate strings are added to an interned strings table. A reference to a duplicate string is returned if a string to be created is already in the string cache file. | 01-19-2012 |
Andrew Russell Low, Ottawa CA
| Patent application number | Description | Published |
|---|---|---|
| 20110131561 | Memory Optimization of Virtual Machine Code by Partitioning Extraneous Information - A method, computer program product, and system for memory optimization by partitioning extraneous information from executable virtual machine code or interpreted code. The extraneous information may be stored separately, or accessed from the original code if needed for debugging or servicing the code in the field. This approach optimizes memory usage by reducing memory footprint while maintaining accessibility of the non-executable information for debugging and other processes necessary for servicing code in the field. | 06-02-2011 |
Anita Low, Richmond Hill CA
| Patent application number | Description | Published |
|---|---|---|
| 20090150172 | METHOD AND SYSTEM FOR COMMUNICATING PATIENT INFORMATION - A method of communicating a patient care message is disclosed. The method comprises inputting patient information into the patient care message; inputting an urgency indicator into the patient care message; inputting health condition information into the patient care message; transmitting the patient care message electronically, wherein the patient care message comprises the patient information, the urgency indicator, and the health condition information. | 06-11-2009 |
| 20110320221 | METHOD AND SYSTEM FOR COMMUNICATING PATIENT INFORMATION - A method of communicating a patient care message is disclosed. The method comprises inputting patient information into the patient care message; inputting an urgency indicator into the patient care message; inputting health condition information into the patient care message; transmitting the patient care message electronically, wherein the patient care message comprises the patient information, the urgency indicator, and the health condition information. | 12-29-2011 |
Arthur John Low, Chelsea CA
| Patent application number | Description | Published |
|---|---|---|
| 20100064116 | METHOD AND SYSTEM FOR PACKET ENCRYPTION - A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is no next process for a packet at which time it is provided to an output port. | 03-11-2010 |
David P. Low, Amherstburg CA
| Patent application number | Description | Published |
|---|---|---|
| 20120068658 | System And Method For Setting Machine Limits - A system and method for setting machine limits include setting a limit for a machine parameter, setting a temporal operating range for the machine, and setting a temporal step. The machine is operated over the operating range and the machine parameter is measured. A first new limit for the machine parameter is set based at least in part on the measurements over the operating range. The operating range is advanced by the temporal step, and the machine parameter continues to be measured. Another new limit for the machine parameter is set based at least in part on the measurements over the operating range after the operating range has been advanced. | 03-22-2012 |
Trevor Low, North Vancouver CA
| Patent application number | Description | Published |
|---|---|---|
| 20080236439 | SEMI-RIGID RAILCAR COVER - A cover for open top railcars may be alternatively locked into place over the railcar top opening, or rotated on hinges to either side of the railcar to provide access to the entire top of the railcar. The cover may be compressed against either side of the railcar to allow the car to move between structural or other elements of loading or unloading facilities. | 10-02-2008 |
Victor Low, Pointe Claire CA
| Patent application number | Description | Published |
|---|---|---|
| 20100114388 | METHOD AND SYSTEM FOR CONTROLLING A DOUBLY-FED INDUCTION MACHINE - The present invention relates to a method and system for controlling a doubly-fed induction machine. In operation a rotor current vector is processed with a rotor position estimate vector. A scalar error quantity is the determined in dependence upon a stator current vector and the processed rotor current vector. The scalar error quantity is integrated and an estimate of the rotor angular frequency is determined in dependence upon the integrated scalar error quantity. To obtain a rotor position estimate, the estimate of the rotor angular frequency is integrated and a rotor position estimate vector is determined in dependence upon the rotor position estimate. The rotor position estimate vector is then provided for processing the rotor current vector. As output signals a signal indicative of the rotor position estimate vector and a signal indicative of the estimate of the rotor angular frequency are provided for controlling the doubly-fed induction machine. | 05-06-2010 |
Yip Seng Low, Thornhill CA
| Patent application number | Description | Published |
|---|---|---|
| 20090032940 | Conductor Bump Method and Apparatus - Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer. | 02-05-2009 |
| 20100102457 | Hybrid Semiconductor Chip Package - Various apparatus and method of packaging semiconductor chips are disclosed. In one aspect, a method of manufacturing is provided that includes placing a semiconductor chip package into a mold. The semiconductor chip package includes a substrate that has a side and a first semiconductor chip coupled to the side in spaced apart relation to define a space between the first semiconductor chip and the side. A second semiconductor chip is mounted on the first semiconductor chip. At least one conductor wire is electrically coupled to the second semiconductor chip and the substrate. A molding material is introduced into the mold to flow into the space and establish an underfill and encapsulate the first semiconductor chip and the second semiconductor chip. | 04-29-2010 |
| 20100155938 | FACE-TO-FACE (F2F) HYBRID STRUCTURE FOR AN INTEGRATED CIRCUIT - An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL. | 06-24-2010 |
| 20110024898 | METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS - A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m≠n is disclosed. The method includes forming (m−n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials. | 02-03-2011 |
| 20110057307 | Semiconductor Chip with Stair Arrangement Bump Structures - Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first conductor structure on a first side of a semiconductor chip and forming a second conductor structure in electrical contact with the first conductor structure. The second conductor structure is adapted to be coupled to a solder structure and includes a stair arrangement that has at least two treads. | 03-10-2011 |
| 20110133338 | CONDUCTOR BUMP METHOD AND APPARATUS - Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer. | 06-09-2011 |
| 20110147061 | Circuit Board with Via Trace Connection and Method of Making the Same - Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor trace with a first segment that does not include a via land. A first via is formed on the first segment. | 06-23-2011 |
| 20110225813 | METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS - A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m≠n is disclosed. The method includes forming (m−n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials. | 09-22-2011 |