| Patent application number | Description | Published |
|---|
| 20080307371 | Manufacturing Aware Design and Design Aware Manufacturing - Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC based on the designed IC layout. Some embodiments concurrently select an optimal pair of wiring and illumination configurations. Other embodiments select an illumination configuration based on the selected wiring configuration. Yet other embodiments select a wiring configuration based on the selected illumination configuration. In some embodiments, selecting the illumination configuration entails selecting at least one stepper lens for the IC layout, where the stepper lens illuminates at least one mask for at least one particular layer of the IC layout. In some embodiments, this selection entails selecting a stepper lens for each particular layer of the IC layout. Also, in some embodiments, selecting the wiring configuration entails defining the width and/or spacing of the routes along different directions on at least one particular wiring layer of the IC layout. In some embodiments, this selection entails selecting width and/or spacing of routes along different directions on each particular layer of the IC layout. | 12-11-2008 |
| 20090031271 | ROBUST DESIGN USING MANUFACTURABILITY MODELS - The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products. | 01-29-2009 |
| 20090077520 | Method and System for Representing Manufacturing and Lithography Information for IC Routing - A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed. | 03-19-2009 |
| 20090077521 | Method and System for Representing Manufacturing and Lithography Information for IC Routing - A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed. | 03-19-2009 |
| 20090199145 | Method for Accounting for Process Variation in the Design of Integrated Circuits - A method to simulate an electronic circuit includes determining process parameters and a process variation for each process parameter, and determining a value for each of a plurality of components of the circuit as a function of the process variations. | 08-06-2009 |
| 20100180247 | AWARE MANUFACTURING OF INTEGRATED CIRCUITS - Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit (“IC”). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings. | 07-15-2010 |
| 20110046767 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PREPARING MULTIPLE LAYERS OF SEMICONDUCTOR SUBSTRATES FOR ELECTRONIC DESIGNS - Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks. | 02-24-2011 |
