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Lou, Shanghai
Di Lou, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20120098431 | GRID FOR ILLUMINATION APPARATUS - The invention relates to illumination, especially to a grid for illumination apparatus. This invention provides a grid ( | 04-26-2012 |
Dongming Lou, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20100246739 | METHOD FOR MEASURING PHASE LOCKED LOOP BANDWIDTH PARAMETERS FOR HIGH-SPEED SERIAL LINKS - A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator, determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency. | 09-30-2010 |
Junshan Lou, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20090109714 | POWER SUPPLY MODULE ADAPTED TO POWER A CONTROL CIRCUIT OF A SWITCHING MODE POWER SUPPLY - A power supply module to power the control circuit of a switching mode power supply is provided. Based on the determination of whether the switching mode power supply is under a light or open load condition, the power supply module can dynamically provide the power to the control circuit of the switching mode power supply. Therefore, the performance of the power supply can be increased and the power loss can be decreased when the switching mode power supply is under a light or open load. | 04-30-2009 |
| 20110051464 | Compensation Device For Synchronous Rectifier Control And Method Thereof - The configurations of a compensation device configured in a circuit having a synchronous rectifier (SR), a controller and a load, and a compensation method thereof are provided in the present invention. In the proposed circuit, the SR includes a first terminal, a first inductor electrically connected to the first terminal in series, a second terminal and a second inductor electrically connected to the second terminal in series, the controller is coupled to the first and the second inductors, and the device includes a voltage source having a positive terminal coupled to the controller and a negative terminal coupled to the second inductor and providing a compensation voltage to reduce or eliminate the influence of the first and the second inductors towards a voltage value across the first and the second terminals. | 03-03-2011 |
Kang-Zhen Lou, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20120136484 | DATA CENTER - A data center is provided. The data center includes a plurality of racks, a container management network and a container management module. Each of the racks includes a rack management module and a plurality of server modules. The rack management module is used for receiving an operation status of the corresponding server module. The container management network is connected to the rack management module and the server module. The container management module is connected to each rack through container management network to receive the operation status for controlling and managing each rack according to the operation status. | 05-31-2012 |
| 20120136489 | RACK SERVER SYSTEM - A rack server system is provided. The rack server system includes a plurality of server modules, a plurality of fan modules, a rack management network and a rack management module. Each of the server modules comprises a baseboard management controller (BMC) to monitor and manage a work status of the corresponding server module. Each of the fan modules includes a plurality of fans. The rack management network is connected to the BMC of each server module. The rack management module receives the work status from the BMC of each server module through the rack management network to control and manage the server modules and to control speed of the fan modules. | 05-31-2012 |
| 20120136978 | RACK SERVER SYSTEM AND MANAGEMENT METHOD OF THE SAME - A rack server system management method adapted in a rack server system is provided. The rack server system management method comprises the steps as follows. The first information of a plurality of servers in the rack server system and the second information of a plurality of fan modules in the rack server system are updated every predetermined time period by a document management unit. A rack management module retrieves the first and the second information through polling the document management unit. The rack management module retrieves temperature values of the servers from the first information and adjusts the speed of the fan module according to the second information. A rack server system is disclosed herein as well. | 05-31-2012 |
Liguang Lou, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20100113498 | NOVEL VINBLASTINE DERIVATIVES, THEIR PREPARATION, USE AND PHARMACEUTICAL COMPOSITIONS COMPRISING THE SAID DERIVATIVES - The invention provides vinblastine derivatives represented by the following formula 1 or their physiologically acceptable salts, their preparation, use and pharmaceutical compositions comprising the said derivatives. The said vinblastine derivatives show inhibiting activities against tumor cell lines and can be used as medicaments for treating malignant tumors. | 05-06-2010 |
| 20110112061 | PYRIDAZINONES, THE PREPARATION AND THE USE THEREOF - The present invention relates to a class of pyridazinones of formula I, which comprises 6-[3-(trifluoromethyl)phenyl]pyridazin-3(2H)-one as a mother nucleus, the preparation method thereof and the use thereof in manufacturing medicaments against tumors, especially liver cancer. | 05-12-2011 |
Yin Lou, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20110208426 | Map-Matching for Low-Sampling-Rate GPS Trajectories - This disclosure describes a map-matching module that supports a Global Positioning System (GPS) and provides a user with a best match trajectory corresponding to GPS sampling points taken at a low sampling rate. The best match trajectory is based upon a spatial-temporal analysis. | 08-25-2011 |
| 20110208429 | Route Computation Based on Route-Oriented Vehicle Trajectories - Techniques for providing a route based on route-oriented vehicle trajectories are described. This disclosure describes receiving GPS logs and extracting route-oriented vehicle trajectory content from the GPS log data to pertain to a single trip. Next, the process maps each route-oriented vehicle trajectory to a corresponding road segment to construct a landmark graph. A landmark is a road segment frequently visited by route-oriented vehicles. The process includes receiving a user query with a starting point and a destination point; searching the landmark graph for a sequence of landmarks with corresponding transition times and a least amount of travel time. Then the process identifies and connects sets of road segments between each pair of consecutive landmarks, and displays a route to a user with a nearest landmark to the starting point, other landmarks along the route, and another nearest landmark to the destination point. | 08-25-2011 |
Yingying Lou, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20080233748 | ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY - A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the layer of material. The resist mask does not cover the trench. The layer of material is isotropically etched. An etch depth may be determined from a characteristic of etching of the material underneath the mask. Such a method may be used for forming SGT structures. The wafer may comprise a layer of material disposed on at least a portion of a surface of semiconductor wafer; a resist mask comprising an angle-shaped test portion disposed over a portion of the layer of material; and a ruler marking on the surface of the substrate proximate the test portion. | 09-25-2008 |
| 20080272371 | RESISTANCE-BASED ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY - A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut D | 11-06-2008 |
| 20090166621 | RESISTANCE-BASED ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY - A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut D | 07-02-2009 |
| 20100099230 | Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer - This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide. | 04-22-2010 |
| 20120001176 | ETCH DEPTH DETERMINATION STRUCTURE - A semiconductor device wafer includes a test structure. The test structure includes a layer of material having an angle-shaped test portion disposed on at least a portion of a surface of the semiconductor wafer. A ruler marking on the surface of the semiconductor wafer proximate the test portion is adapted to facilitate measurement of a change in length of the test portion. | 01-05-2012 |