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Losee, US
Becky Losee, Cedar Hills, UT US
| Patent application number | Description | Published |
|---|---|---|
| 20080199997 | Methods of Forming Inter-poly Dielectric (IPD) Layers in Power Semiconductor Devices - A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities. | 08-21-2008 |
| 20100015769 | Power Device With Trenches Having Wider Upper Portion Than Lower Portion - A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and outer portions extending directly underneath the masking layer. The outer portions form outer sections of corresponding trenches. Additional portions of the silicon layer are removed through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches. A first doped region of a first conductivity type is formed in an upper portion of the silicon layer. An insulating layer is formed within each trench, and extends directly over a portion of the first doped region adjacent each trench sidewall. Silicon is removed from adjacent each trench until, of the first doped region, only the portions adjacent the trench sidewalls remain. The remaining portions of the first doped region adjacent the trench sidewalls form source regions which are self-aligned to the trenches. | 01-21-2010 |
| 20110003449 | Power Device With Trenches Having Wider Upper Portion Than Lower Portion - A method of forming a semiconductor device includes the following. Removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer; and forming source regions in the silicon layer adjacent the trench sidewall such that the source regions extend into the portions of the silicon layer directly over which the trench sidewalls extend. | 01-06-2011 |
Becky Losee, Orem, UT US
| Patent application number | Description | Published |
|---|---|---|
| 20090111227 | Method for Forming Trench Gate Field Effect Transistor with Recessed Mesas Using Spacers - A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region. The second silicon region is recessed through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain. The remaining portions of the second silicon region form source regions. | 04-30-2009 |
Paul Losee, Layton, UT US
| Patent application number | Description | Published |
|---|---|---|
| 20100214118 | SYSTEM AND METHOD FOR TRACKING A PERSON - A system and method for tracking a person using a deduced reckoning device is disclosed. The method includes the operation of selecting an initial location of the person. The person's movement along a path is then monitored using directional sensors, including a digital magnetic compass, at least one accelerometer, at least one magnetometer, at least one gyroscope, and an altimeter. The person's changing location is recorded based on a change in outputs of the directional sensors that occur during the person's movement. The person's changing location is transmitted to a command and control center. The person's changing location is then displayed on a graphical user interface at the command and control center. | 08-26-2010 |
Peter Almern Losee, Clifton Park, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100277868 | INSULATED METAL SUBSTRATES INCORPORATING ADVANCED COOLING - A power module includes one or more semiconductor power devices bonded to an insulated metal substrate (IMS). A plurality of cooling fluid channels is integrated into the IMS. | 11-04-2010 |
| 20100308340 | SEMICONDUCTOR DEVICE HAVING A BURIED CHANNEL - Provided is a device that includes a semiconductor body having a surface. Source and drain regions with effective dopant populations of a first polarity can be disposed adjacent to the surface and spaced apart from one another. A channel region with an effective dopant population of the first polarity can extend between the source and drain regions while being spaced apart from the surface. A gate region with an effective dopant population of a second polarity and first effective dopant density can extend between the source and drain regions and be disposed between the channel region and the surface. A gate contact region can be disposed between the source and drain regions and adjacent to the surface. The gate contact region can have an effective dopant population of the second polarity and a second effective dopant density greater than the first effective dopant density. | 12-09-2010 |
| 20110024765 | SILICON CARBIDE SEMICONDUCTOR STRUCTURES, DEVICES AND METHODS FOR MAKING THE SAME - There are provided semiconductor structures and devices comprising silicon carbide (SiC) and methods for making the same. The structures and devices comprise a base or shielding layer, channel and surface layer, all desirably formed via ion implantation. As a result, the structures and devices provided herein are hard, “normally off” devices, i.e., exhibiting threshold voltages of greater than about 3 volts. | 02-03-2011 |
Peter Almern Losee, Rensselaer, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100200931 | MOSFET DEVICES AND METHODS OF MAKING - A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence. | 08-12-2010 |