Patent application number | Description | Published |
20120264911 | System and Method for Processing Reactor Polymerization Effluent - A method of treating a polymerization reactor effluent stream comprising recovering the reactor effluent stream from the polymerization reactor, flashing the reactor effluent stream to form a flash gas stream, separating the flash gas stream into a first top stream, a first bottom stream, and a side stream, wherein the side stream substantially comprises hexane, separating the first top stream into a second top stream and a second bottom stream, wherein the second bottom stream substantially comprises isobutene, and separating the second top stream into a third top stream and a third bottom stream; wherein the third top stream substantially comprises ethylene, and wherein the third bottom stream is substantially free of olefins. | 10-18-2012 |
20130101469 | System and Method for Processing Reactor Polymerization Effluent - A method of treating a polymerization reactor effluent stream comprising recovering the reactor effluent stream from the polymerization reactor, flashing the reactor effluent stream to form a flash gas stream, separating the flash gas stream into a first top stream, a first bottom stream, and a side stream, wherein the side stream substantially comprises hexane, separating the first top stream into a second top stream and a second bottom stream, wherein the second bottom stream substantially comprises isobutane, and separating the second top stream into a third top stream and a third bottom stream; wherein the third top stream substantially comprises ethylene, and wherein the third bottom stream is substantially free of olefins. | 04-25-2013 |
20130280137 | System and Method for Processing Reactor Polymerization Effluent - A method of treating a polymerization reactor effluent stream comprising recovering the reactor effluent stream from the polymerization reactor, flashing the reactor effluent stream to form a flash gas stream, separating the flash gas stream into a first top stream, a first bottom stream, and a side stream, wherein the side stream substantially comprises hexane, separating the first top stream into a second top stream and a second bottom stream, wherein the second bottom stream substantially comprises isobutane, and separating the second top stream into a third top stream and a third bottom stream; wherein the third top stream substantially comprises ethylene, and wherein the third bottom stream is substantially free of olefins. | 10-24-2013 |
20130284580 | System and Method for Processing Reactor Polymerization Effluent - A method of treating a polymerization reactor effluent stream comprising recovering the reactor effluent stream from the polymerization reactor, flashing the reactor effluent stream to form a flash gas stream, separating the flash gas stream into a first top stream, a first bottom stream, and a side stream, wherein the side stream substantially comprises hexane, separating the first top stream into a second top stream and a second bottom stream, wherein the second bottom stream substantially comprises isobutane, and separating the second top stream into a third top stream and a third bottom stream; wherein the third top stream substantially comprises ethylene, and wherein the third bottom stream is substantially free of olefins. | 10-31-2013 |
Patent application number | Description | Published |
20080198772 | System and method for transmitter leak-over cancellation with closed loop optimization - The present disclosure relates generally to systems and methods for transmitter leak-over cancellation. In one example, a method includes transmitting a signal via a transmit chain in a wireless device, where a portion of the signal leaks over into a receive chain of the wireless device. A portion of the signal is diverted from the transmit chain into cancellation circuitry coupled to the receive chain to manipulate an amplitude and phase of the portion before combining the manipulated portion with the signal and other portion to at least partially cancel interference caused by the leak-over portion. After downconverting, a remainder portion is filtered from the received signal. A power level of the remainder portion is detected and compared to a threshold value. An amplitude and phase configuration of the cancellation circuitry is modified based on a result of comparing the power level to the threshold value. | 08-21-2008 |
20080198773 | System and method for transmitter leak-over cancellation - The present disclosure relates generally to systems and methods for transmitter leak-over cancellation. In one example, a method includes transmitting a signal via a transmit chain in a wireless device, where a portion of the signal leaks over into a receive chain of the wireless device and generates higher order products that interfere with a signal being received by the wireless device. A portion of the signal from the transmit chain is diverted into cancellation circuitry coupled to the receive chain prior to a location in the transmit chain where leak-over occurs, and an amplitude and phase of the portion is manipulated. The manipulated portion is combined with the received signal and other portion to at least partially cancel interference caused by the portion leaking over into the receive chain. | 08-21-2008 |
20130170581 | QUADRATURE DIGITAL-IF TRANSMITTER WITHOUT INTER-STAGE SAW FILTER AND DEVICES USING SAME - An RF transmitter comprises a digital-to-IF circuit block configured to receive a digital in-phase baseband signal and a digital quadrature baseband signal and to up-convert the digital in-phase and quadrature baseband signals to a digital in-phase IF signal and to a digital quadrature IF signal. The wireless RF transmitter further comprises an IF-to-RF circuit block configured to convert the digital in-phase and quadrature IF signals to analog signals and to up-convert the analog in-phase and quadrature IF signals to an RF output signal. The digital-to-IF circuit block comprises pre-compensation circuitry configured to reduce analog impairments associated with the IF-to-RF circuit block. | 07-04-2013 |
20140198689 | APPARATUS AND METHOD FOR MIXED SIGNAL SPREAD SPECTRUM RECEIVING TECHNIQUE - An apparatus and method for mixed signal spread spectrum receiving and spectrum aggregation in a receiver having at least one antenna respectively receiving at least one signal are provided. The method includes modulating the at least one signal received by the receiver with at least one unique orthogonal pseudorandom (PN) code, downconverting the at least one modulated signal into at least one baseband signal, combining the at least baseband signal into an overlaid baseband signal and filtering the overlaid baseband signal, converting the overlaid baseband signal from an analog signal into a digital baseband signal, splitting the digital baseband signal into a plurality of signal paths each having the entirety of the digital baseband signal, applying one of the at least one unique orthogonal PN code to each of the plurality of signal paths, and multiplexing the plurality of signal paths into a combined digital baseband signal. | 07-17-2014 |
20140220908 | ADAPTIVE TRANSMITTER LEAKAGE CANCELATION IN A TRANSCEIVER - An apparatus and method cancel transmitter leakage. The method includes generating a leakage cancelation signal by processing a downconverted signal for cancelation of a leakage signal caused by a transmitter and upconverting the downconverted signal to a radio frequency of the transmitter. The method also includes canceling at least some of the leakage signal in a received signal using the leakage cancelation signal. | 08-07-2014 |
20140327594 | APPARATUS AND METHOD FOR MATCHING IMPEDANCE - An apparatus for matching impedance for use in a wireless communication is provided. The apparatus includes a forward path carrying a transmission signal to an antenna. The apparatus further comprises a quadrature feedback path configured to extract and feed back in-phase and quadrature phase components from each of a forward signal being transmitted toward the antenna and a reverse signal reflected from the antenna. A tunable matching network (TMN) is coupled to the forward path, having a plurality of tunable elements for matching an internal impedance to an impedance of the antenna. A controller is configured to calculate TMN input impedance's amplitude and phase based on the in-phase and quadrature phase components from each of the forward signal and the reverse signal. | 11-06-2014 |
20140328433 | APPARATUS AND METHOD FOR ENVELOPING TRACKING CALIBRATION - An apparatus for envelope tracking calibration for use in a wireless communication is provided. The apparatus includes a transmission signal path configured to carry a transmission signal to an antenna. An envelope signal path configured to feed an envelope signal with an envelope tracking power amplifier. A controller is configured to transmit a normal envelope signal being generated in a normal operation mode and measure a first Adjacent Channel Leakage Ratio (ACLR) corresponding to the normal envelope signal. The controller is further configured to transmit a comparison envelope signal being generated in a comparison operation mode and measure a second ACLR corresponding to the comparison envelope signal. The controller is configured to calculate a time misalignment between the transmission signal path and the envelope signal path based on a difference between the first and second ACLRs. | 11-06-2014 |
Patent application number | Description | Published |
20100110807 | Bitline Leakage Detection in Memories - An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage. | 05-06-2010 |
20100208536 | Structure and Methods for Measuring Margins in an SRAM bit - Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design. | 08-19-2010 |
20100232242 | Method for Constructing Shmoo Plots for SRAMS - A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array circuitry to determine the type of failure that may have occurred at each test voltage measurement point. | 09-16-2010 |
20110051539 | Method and structure for SRAM VMIN/VMAX measurement - A parametric test circuit is disclosed (FIG. | 03-03-2011 |
20110051540 | Method and structure for SRAM cell trip voltage measurement - A parametric test circuit is disclosed (FIG. | 03-03-2011 |
20110158017 | METHOD FOR MEMORY CELL CHARACTERIZATION USING UNIVERSAL STRUCTURE - A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type. The method further includes conducting a circuit element test on a circuit element in the set of circuit elements, where in the circuit element test the first and second supply nodes are not connected together, each terminal of the circuit element is directly forced with an electrical quantity, and an electrical quantity is directly measured from a terminal of the circuit element. Further, the method includes conducting at least one of a static noise margin test or a full cell test on the memory base cell. | 06-30-2011 |
20110158018 | Structure and Methods for Measuring Margins in an SRAM Bit - Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design. | 06-30-2011 |
20110299349 | Margin Testing of Static Random Access Memory Cells - A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis. | 12-08-2011 |
20120014195 | SRAM with buffered-read bit cells and its testing - An SRAM with buffered-read bit cells is disclosed (FIGS. | 01-19-2012 |
20120104510 | CMOS PROCESS TO IMPROVE SRAM YIELD - An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. | 05-03-2012 |
20120106225 | Array-Based Integrated Circuit with Reduced Proximity Effects - An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array. | 05-03-2012 |
20120243354 | Repairing Soft Failures in Memory Cells in SRAM Arrays - An embodiment of the invention provides a method of repairing soft failures in memory cells of an SRAM array. The SRAM array is tested to determine the location and type of soft failures in the memory cells. An assist circuit is activated that changes a voltage in a group of memory cells with the same type of soft failure. The change in voltage created by the assist circuit repairs the soft failures in the group. The group may be a word line or a bit line. The type of soft failures includes a failure during a read of a memory cell and a failure during the write of a memory cell. | 09-27-2012 |
20120307550 | Asymmetric Static Random Access Memory Cell with Dual Stress Liner - A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Each memory cell includes a pair of cross-coupled CMOS inverters, and corresponding pass gates for coupling the cross-coupled storage nodes to first and second bit lines. Asymmetry is incorporated into each memory cell by constructing one of the inverter transistors or the pass-gate transistor using the stress liner with opposite stress characteristics from its opposing counterpart. For example, both of the p-channel load transistors and one of the n-channel driver transistors in each memory cell may be constructed with a compressive nitride liner layer while the other driver transistor is constructed with a tensile nitride liner layer. In another implementation, one of the n-channel pass-gate transistors is constructed with a compressive nitride liner layer while the other pass-gate transistor is constructed with a tensile nitride liner layer. Improved cell stability due to the resulting asymmetric behavior is implemented in a cost-free manner. | 12-06-2012 |
20120324314 | Low Power Retention Random Access Memory with Error Correction on Wake-Up - Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode. | 12-20-2012 |
20130021864 | Array Power Supply-Based Screening of Static Random Access Memory Cells for Bias Temperature Instability - A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified. | 01-24-2013 |
20130028036 | Method of Screening Static Random Access Memories for Unstable Memory Cells - A screening method for testing solid-state memories for the effects of long-term shift and random telegraph noise (RTN). In the context of static random access memories (SRAMs), each memory cell in the array is functionally tested with a bias voltage (e.g., the cell power supply voltage) at a severe first guardband sufficient to account for worst case long-term shift and RTN effects. Cells failing the first guardband are then repeatedly tested with the bias voltage at a second guardband, less severe than the first guardband; if the tested cells pass this second guardband, the suspect cells are considered to not be vulnerable to RTN effects. Over-screening due to an unduly severe guardband is avoided, while still screening vulnerable memories from the population. | 01-31-2013 |
20130044536 | ARRAY-BASED INTEGRATED CIRCUIT WITH REDUCED PROXIMITY EFFECTS - An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array. | 02-21-2013 |
20130058177 | Method of Screening Static Random Access Memory Cells for Positive Bias Temperature Instability - A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (V | 03-07-2013 |
20130094314 | SRAM POWER REDUCTION THROUGH SELECTIVE PROGRAMMING - A method of programming a memory array having plural subarrays is disclosed. (FIG. | 04-18-2013 |
20130176772 | Electrical Screening of Static Random Access Memories at Varying Locations in a Large-Scale Integrated Circuit - A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing, are disclosed. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed. | 07-11-2013 |
20130182490 | Static Random Access Memory Cell with Single-Sided Buffer and Asymmetric Construction - Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature. | 07-18-2013 |
20130320458 | Static Random-Access Memory Cell Array with Deep Well Regions - An integrated circuit including a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area. Bias conductors may contact the grids to apply the desired well bias voltages, for example in well-tie regions or peripheral circuitry adjacent to the memory cell array. | 12-05-2013 |
20130343136 | SRAM WITH BUFFERED-READ BIT CELLS AND ITS TESTING - An SRAM with buffered-read bit cells is disclosed (FIGS. | 12-26-2013 |
20140078819 | STATIC RANDOM ACCESS MEMORY CELL WITH SINGLE-SIDED BUFFER AND ASYMMETRIC CONSTRUCTION - Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature. | 03-20-2014 |
20140126277 | SRAM WITH BUFFERED-READ BIT CELLS AND ITS TESTING - An SRAM with buffered-read bit cells is disclosed ( | 05-08-2014 |
20140346609 | CMOS Process To Improve SRAM Yield - An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. | 11-27-2014 |
Patent application number | Description | Published |
20100320510 | Interfacial Barrier for Work Function Modification of High Performance CMOS Devices - A semiconductor structure may include a semiconductor bulk region with a gate stack on the semiconductor bulk region. The source region and the drain region in the semiconductor bulk region may be located on opposing sides of a channel region below the gate stack. An interfacial layer coupled to the channel region may modify a workfunction of a metal-semiconductor contact. In a MOSFET, the metal-semiconductor contact may be between a metal contact and the source region and the drain region. In a Schottky barrier-MOSFET, the metal-semiconductor contact may be between a silicide region in the source region and/or the drain region and the channel region. The interfacial layer may use a dielectric-dipole mitigated scheme and may include a conducting layer and a dielectric layer. The dielectric layer may include lanthanum oxide or aluminum oxide used to tune the workfunction of the metal-semiconductor contact. | 12-23-2010 |
20110215425 | TUNNELING FIELD-EFFECT TRANSISTOR WITH DIRECT TUNNELING FOR ENHANCED TUNNELING CURRENT - Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide. | 09-08-2011 |
20110278670 | Apparatus, System, and Method for Tunneling Mosfets Using Self-Aligned Heterostructure Source and Isolated Drain - Apparatuses, systems, and methods for tunneling MOSFETs (TFETs) using a self-aligned heterostructure source and isolated drain. TFETs that have an abrupt junction between source and drain regions have an increased probability of carrier direct tunneling (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. | 11-17-2011 |
20130230954 | TUNNELING FIELD-EFFECT TRANSISTOR WITH DIRECT TUNNELING FOR ENHANCED TUNNELING CURRENT - Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide. | 09-05-2013 |
20130320427 | GATED CIRCUIT STRUCTURE WITH SELF-ALIGNED TUNNELING REGION - A tunnel field-effect transistor is provided, which includes a fin-shaped, source-drain circuit structure with a source region and a drain region. The circuit structure is angled in cross-sectional elevation, and includes a first portion and a second portion. The first portion extends away from the second portion, and the source region is disposed in the first or second portion, and the drain region is disposed in the other of the first or second portion. The transistor further includes a gate electrode for gating the circuit structure and a self-aligned tunneling region. The tunneling region is self-aligned to at least a portion of the circuit structure and extends between the gate electrode and the first or second portion of the fin-shaped circuit structure, and the self-aligned tunneling region is at least partially disposed in parallel, spaced opposing relation to a control surface of the gate electrode. | 12-05-2013 |
20140054549 | GATED CIRCUIT STRUCTURE WITH ULTRA-THIN, EPITAXIALLY-GROWN TUNNEL AND CHANNEL LAYER - A semiconductor device and tunnel field-effect transistor, and methods of fabrication thereof are provided. The device includes first and second semiconductor regions, an intermediate region, and an epitaxial layer. The intermediate region separates the first and second semiconductor regions, and the epitaxial layer extends at least partially between the first and second regions over or alongside of the intermediate region. A gate electrode is provided for gating the circuit structure. The epitaxial layer is disposed to reside between the gate electrode and at least one of the first semiconductor region, the second semiconductor region, or the intermediate region. The epitaxial layer includes an epitaxially-grown, ultra-thin body layer of semiconductor material with a thickness less than or equal to 15 nanometers. Where the semiconductor device is a tunneling field-effect transistor, the intermediate region may be a large band-gap semiconductor region, with a band-gap greater than that of the epitaxial layer. | 02-27-2014 |