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| 20080273880 | Redundant channel implementation to extend optical transceiver lifetime and relibility - Embodiments introduce redundant optical channels to significantly extend the lifetime of parallel optical transceivers. A plurality of transmitters, N, transmit on a plurality of optical channels, where N is an integer number of optical channels greater than 1. One or more redundant channels, M, are also provided. N+M multiple input shift registers provide multiple paths for signals from each of the transmitters to connect to N+M laser diodes. In the event up to M of the N+M laser diodes fail, the multiple input shift registers connect the N transmitters to functioning ones of the N+M laser diodes thus extending the life of the device. A corresponding scheme is also described for the receiver side. | 11-06-2008 |
| 20080304527 | Controlling a bias current for an optical source - In one embodiment, the present invention includes an apparatus having a current mirror with a current source coupled to a first terminal and an output current to flow from an output terminal, a laser coupled to the output terminal to be biased by the output current, and a comparator to compare a voltage of the first terminal to the voltage of the output terminal and gate the current mirror based on the comparison. Other embodiments are described and claimed. | 12-11-2008 |
| 20090074123 | Phase/Frequency Detector and Charge Pump Architecture for Referenceless Clock and Data Recovery (CDR) Applications - A stream of data may flow over a fiber or other medium without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Embodiments describe clock and data recovery (CDR) circuits which may sample a data signal at a plurality of sampling points to partition a clock cycle into four phase regions P | 03-19-2009 |
| 20090208226 | Bang-bang architecture - In one embodiment, the present invention includes an apparatus having a voltage controlled oscillator (VCO) to generate a first clock signal having a frequency controlled by a bias current coupling ratio of first and second bias currents, and a control circuit coupled to the VCO to generate a first pair of control signals to adjust the bias current coupling ratio. Other embodiments are described and claimed. | 08-20-2009 |
| 20090243729 | CONTROLLING OVERLOAD OF A TRANSIMPEDANCE AMPLIFIER IN AN OPTICAL TRANSCEIVER - Briefly, in accordance with one or more embodiments, a transimpedance amplifier of an optical transceiver or the like has a feedback element in a feedback arrangement and is capable of receiving an electrical current from an optical-to-electrical converter to generate an output voltage in response to the electrical current. A control circuit coupled to the feedback element is capable of providing a control signal to control a bias current of the transimpedance amplifier to maintain DC current flowing through the feedback element at or near zero by changing the bias current in response to the control circuit detecting a non-zero DC current flowing through the feedback element. | 10-01-2009 |
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| 20080260071 | Methods and Apparatus for Frequency Synthesis with Feedback Interpolation - A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed. | 10-23-2008 |
| 20110228889 | Repeater Architecture with Single Clock Multiplier Unit - A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A first interpolator, coupled to one or more of the flip-flops, receives the sampled input data. The controller, coupled to the first interpolator, controls the first interpolator by providing phase information regarding the input data to the first interpolator. The circuit reduces any jitter transferred from the input path to an output path. | 09-22-2011 |
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| 20090155370 | METHODS AND COMPOSITIONS FOR SELECTIVELY REMOVING POTASSIUM ION FROM THE GASTROINTESTINAL TRACT OF A MAMMAL - The present invention provides methods and compositions for the treatment of ion imbalances using core-shell composites and compositions comprising such core-shell composites. In particular, the invention provides core-shell particles and compositions comprising potassium binding polymers, and core-shell particles and compositions comprising sodium binding polymers, and in each case, pharmaceutical compositions thereof. Methods of use of the polymeric and pharmaceutical compositions for therapeutic and/or prophylactic benefits are also disclosed. The compositions and methods of the invention offer improved approaches for treatment of hyperkalemia and other indications related to potassium ion homeostasis, and for treatment of hypertension and other indicates related to sodium ion homeostasis. | 06-18-2009 |
| 20090186093 | METHODS FOR PREPARING CORE-SHELL COMPOSITES HAVING CROSS-LINKED SHELLS AND CORE-SHELL COMPOSITES RESULTING THEREFROM - The present invention provides methods and compositions for the treatment of ion imbalances using core-shell composites and compositions comprising such core-shell composites. In particular, the invention provides core-shell particles and compositions comprising potassium binding polymers, and core-shell particles and compositions comprising sodium binding polymers, and in each case, pharmaceutical compositions thereof. Methods of use of the polymeric and pharmaceutical compositions for therapeutic and/or prophylactic benefits are also disclosed. The compositions and methods of the invention offer improved approaches for treatment of hyperkalemia and other indications related to potassium ion homeostasis, and for treatment of hypertension and other indicates related to sodium ion homeostasis. | 07-23-2009 |
| 20110033505 | METHODS AND COMPOSITIONS FOR TREATMENT OF ION IMBALANCES - The present invention provides methods and compositions for the treatment of ion imbalances. In particular, the invention provides compositions comprising sodium-binding polymers and pharmaceutical compositions thereof. Methods of use of the polymeric and pharmaceutical compositions for therapeutic and/or prophylactic benefits are disclosed herein. Examples of these methods include the treatment of hypertension, chronic heart failure, end stage renal disease, liver cirrhosis, chronic renal insufficiency, fluid overload, or sodium overload. | 02-10-2011 |
| 20110276133 | POROUS MATERIALS, METHODS OF MAKING AND USES - The present specification discloses porous materials, methods of forming such porous materials, biocompatible implantable devices comprising such porous materials, and methods of making such biocompatible implantable devices. | 11-10-2011 |
| 20110276134 | SILICONE IMPLANT WITH IMPRINTED TEXTURE - A procedure for manufacturing an implant having a textured silicone surface is disclosed. An example procedure includes forming a component having a silicone surface; pressing a plurality of polymer fibers at least partially into the silicone surface, before the silicone has completely cured; allowing the silicone to at least partially cure with the polymer fibers in the silicone surface; and after the silicone is at least partially cured, removing the polymer fibers from the silicone surface. | 11-10-2011 |
| 20110278755 | POROGEN COMPOSITIONS, METHOD OF MAKING AND USES - The present specification discloses porogen compositions comprising a core material and shell material, methods of making such porogen compositions, methods of forming such porous materials using such porogen compositions, biocompatible implantable devices comprising such porous materials, and methods of making such biocompatible implantable devices. | 11-17-2011 |
| 20110282444 | POROUS MATERIALS, METHODS OF MAKING AND USES - The present specification discloses porous materials, methods of forming such porous materials, biocompatible implantable devices comprising such porous materials, and methods of making such biocompatible implantable devices. | 11-17-2011 |
| 20120041555 | SILICONE IMPLANT WITH IMPRINTED TEXTURE - A procedure for making an implant having a textured silicone surface is disclosed. The method may include the steps of providing a conventional mandrel and applying a pre-formed, polymeric mesh sock to the mandrel. The sock is contacted with a silicone dispersion and the silicone dispersion is at least partially cured with the sock in contact therewith. The silicone dispersion is at least partially cured while the sock is in contact therewith and the sock is them removed, for example, by dissolution, to leave a textured elastomeric material useful as a component of a breast implant shell. | 02-16-2012 |
| 20120077010 | POROUS MATERIALS, METHODS OF MAKING AND USES - The present specification discloses porous materials, methods of forming such porous materials, materials and devices comprising such porous materials, and methods of making such materials and devices. | 03-29-2012 |
| 20120077012 | POROUS MATERIALS, METHODS OF MAKING AND USES - The present specification discloses porous materials, methods of forming such porous materials, materials and devices comprising such porous materials, and methods of making such materials and devices. | 03-29-2012 |
| 20120077891 | POROGEN COMPOSITIONS, METHODS OF MAKING AND USES - Provided are porogen compositions and methods of using such porogen compositions in the manufacture of porous materials, for example, porous silicone elastomers. The porogens generally include comprising a core material and shell material different from the core material. The porogens can be used to form a scaffold for making a resulting porous elastomer when the scaffold is removed. | 03-29-2012 |
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| 20090089560 | INFRASTRUCTURE FOR PARALLEL PROGRAMMING OF CLUSTERS OF MACHINES - GridBatch provides an infrastructure framework that hides the complexities and burdens of developing logic and programming application that implement detail parallelized computations from programmers. A programmer may use GridBatch to implement parallelized computational operations that minimize network bandwidth requirements, and efficiently partition and coordinate computational processing in a multiprocessor configuration. GridBatch provides an effective and lightweight approach to rapidly build parallelized applications using economically viable multiprocessor configurations that achieve the highest performance results. | 04-02-2009 |
| 20100100767 | AUTOMATICALLY CONNECTING REMOTE NETWORK EQUIPMENT THROUGH A GRAPHICAL USER INTERFACE - Embodiments of the present invention provide a method and system for designing a test network in an integrated application, and configuring remote network devices through a network design application to test a network design. One embodiment of the present claimed subject matter is provided as a system for automatically configuring remote network devices to simulate a network connection. The system includes a plurality of computing devices which are physically coupled to one or more network devices, wherein the network devices are automatically configured to comprise a test network corresponding to a remote test network topology design. | 04-22-2010 |
| 20100268764 | METHOD AND SYSTEM FOR CLIENT-SIDE SCALING OF WEB SERVER FARM ARCHITECTURES IN A CLOUD DATA CENTER - A novel web server farm architecture is provided that combines various cloud components and innovatively maximizes their strengths to achieve a scalable, adaptable, load balanced computing architecture. In one embodiment, this architecture includes a storage host for static content hosting, a cluster of virtual machines (operating as web servers) for dynamic content hosting, and a dedicated application engine for monitoring the load of the virtual machines. A browser or end-application user of a web application is first routed to a static anchor page hosted on the storage host. The browser is subsequently presented with a list of virtual machines and data corresponding to their respective current loads. To access dynamic content, the browser is able to select from the virtual machines based in large part on the reported current loads of the virtual machines. Once a virtual machine is selected, the browser may communicate directly with the selected web server. | 10-21-2010 |
| 20100287263 | METHOD AND SYSTEM FOR APPLICATION MIGRATION IN A CLOUD - A method and system for managing an application in a cloud data center by monitoring the bandwidth of a subnet of which the primary operating instance of an application is a member. If a severe deterioration in the bandwidth caused by an over consumption of the subnet resources from other subnet constituents is detected, a suitable secondary instance in an alternate, uncompromised subnet is located and primary operation of the application is transferred from the former primary operating instance to the secondary instance. The secondary instance can be pre-launched or dynamically requisitioned in the cloud data center. | 11-11-2010 |
| 20110265147 | CLOUD-BASED BILLING, CREDENTIAL, AND DATA SHARING MANAGEMENT SYSTEM - A novel solution is provided that utilizes the two-credential characteristics of accessing cloud-hosted data in a portal-oriented enterprise-specific solution. Cloud computing resources may be accessed through a separate, enterprise-specific portal clients used to manage a set of cloud service accounts. Individuals (e.g., employees of the enterprise or company) may access cloud computing resources via an instance of the portal client, and any communication between individuals in an enterprise and cloud services may be facilitated through the portal. Each portal client may also be configured to be compatible with any cloud service vendor. | 10-27-2011 |
| 20120079480 | METHODS FOR MEASURING PHYSICAL CPU UTILIZATION IN A CLOUD COMPUTING INFRASTRUCTURE - Novel techniques are provided to determine concurrent hardware resource usage as expressed in activity performed by hardware processors. A cloud computing consumer can verify the level of the quality of service provided by the physical infrastructure of a cloud, thereby allowing the consumer the ability to request a transfer of the hosting physical infrastructure to a less burdened physical machine. | 03-29-2012 |
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| 20080203056 | METHODS FOR ETCHING HIGH ASPECT RATIO FEATURES - Methods for forming features for high aspect ratio application in etch process are provided in the present invention. In one embodiment, the method for etching a dielectric layer disposed on a substrate includes placing a substrate having a portion of a dielectric layer exposed through a patterned photoresist layer in an etch chamber, supplying a gas mixture containing argon (Ar) gas into the etch chamber, forming a plasma from the gas mixture using dual frequency RF power and etching the exposed dielectric layer using the plasma formed from the gas mixture. | 08-28-2008 |
| 20080230511 | HALOGEN-FREE AMORPHOUS CARBON MASK ETCH HAVING HIGH SELECTIVITY TO PHOTORESIST - In one embodiment of the present invention, a halogen-free plasma etch processes is used to define a feature in a multi-layered masking stack including an amorphous carbon layer. In a particular embodiment, oxygen (O | 09-25-2008 |
| 20080286979 | Method of controlling sidewall profile by using intermittent, periodic introduction of cleaning species into the main plasma etching species - A method of removing a silicon-containing hard polymeric material from an opening leading to a recessed feature during the plasma etching of said recessed feature into a carbon-containing layer in a semiconductor substrate. The method comprises the intermittent use of a cleaning step within a continuous etching process, where at least one fluorine-containing cleaning agent species is added to already present etchant species of said continuous etching process for a limited time period, wherein the length of time of each cleaning step ranges from about 5% to about 100% of the time length of an etch step which either precedes or follows said cleaning step. | 11-20-2008 |
| 20090008033 | METHOD AND APPARATUS FOR SHAPING A MAGNETIC FIELD IN A MAGNETIC FIELD-ENHANCED PLASMA REACTOR - A magnetic field generator which provides greater control over the magnetic field is provided. The magnetic field generator has a plurality of overlapping main magnetic coil sections for forming a magnetic field generally parallel to the top surface of the supporting member. In other embodiments, sub-magnetic coil sections are placed symmetrically around the main magnetic coil sections. | 01-08-2009 |
| 20090142859 | PLASMA CONTROL USING DUAL CATHODE FREQUENCY MIXING - Methods for processing a substrate in a processing chamber using dual RF frequencies are provided herein. In some embodiments, a method of processing a substrate includes forming a plasma of a polymer forming chemistry to etch a feature into a substrate disposed on a substrate support in a process chamber while depositing a polymer on at least portions of the feature being etched. A low frequency and a high frequency RF signal are applied to an electrode disposed in the substrate support. The method further includes controlling the level of polymer formation on the substrate, wherein controlling the level of polymer formation comprises adjusting a power ratio of the high frequency to the low frequency RF signal. | 06-04-2009 |
| 20110115589 | METHOD AND APPARATUS FOR SHAPING A MAGNETIC FIELD IN A MAGNETIC FIELD-ENHANCED PLASMA REACTOR - A magnetic field generator which provides greater control over the magnetic field is provided. The magnetic field generator has a plurality of overlapping main magnetic coil sections for forming a magnetic field generally parallel to the top surface of the supporting member. In other embodiments, sub-magnetic coil sections are placed symmetrically around the main magnetic coil sections. | 05-19-2011 |
| 20110162803 | CHAMBER WITH UNIFORM FLOW AND PLASMA DISTRIBUTION - Embodiments of the present invention provide a recursive liner system that facilitates providing more uniform flow of gases proximate the surface of a substrate disposed within an apparatus for processing a substrate (e.g., a process chamber). In some embodiments, a recursive liner system may include an outer liner having an outer portion configured to line the walls of a process chamber, a bottom portion extending inward from the outer portion, and a lip extending up from the bottom portion to define a well; and an inner liner having a lower portion configured to be at least partially disposed in the well to define, together with the outer liner, a recursive flow path therebetween. | 07-07-2011 |
| 20120024479 | APPARATUS FOR CONTROLLING THE FLOW OF A GAS IN A PROCESS CHAMBER - Apparatus for controlling the flow of a gas in a process chamber is provided herein. In some embodiments, an apparatus for controlling the flow of a gas in a process chamber having a processing volume within the process chamber disposed above a substrate support and a pumping volume within the process chamber disposed below the substrate support may include an annular plate surrounding the substrate support proximate a level of a substrate support surface of the substrate support, wherein the annular plate extends radially outward toward an inner peripheral surface of the process chamber to define a uniform gap between an outer edge of the annular plate and the inner peripheral surface, wherein the uniform gap provides a uniform flow path from the processing volume to the pumping volume. | 02-02-2012 |
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| 20080227963 | Process for preparing glycopeptide phosphonate derivatives - Disclosed are processes for preparing glycopeptide phosphonate derivatives having an amino-containing side chain. Several of the process steps are conducted in a single reaction vessel without isolation of intermediate reaction products, thereby generating less waste and improving the overall efficiency and yield of the process. | 09-18-2008 |
| 20090069534 | Hydrochloride salts of a glycopeptide phosphonate derivative - Disclosed are hydrochloride salts of telavancin having a chloride ion content of from about 2.4 wt. % to about 4.8 wt. %. The disclosed salts have improved stability during storage at ambient temperatures compared to other hydrochloride salts. Also disclosed are processes for preparing such salts. | 03-12-2009 |
| 20090155209 | NOVEL MACROCYCLIC INHIBITORS OF HEPATITIS C VIRUS REPLICATION - The embodiments provide compounds of the general Formula I, as well as compositions, including pharmaceutical compositions, comprising a subject compound. The embodiments further provide treatment methods, including methods of treating a hepatitis C virus infection and methods of treating liver fibrosis, the methods generally involving administering to an individual in need thereof an effective amount of a subject compound or composition. | 06-18-2009 |
| 20100261716 | INDAZOLE-CARBOXAMIDE COMPOUNDS AS 5-HT4 RECEPTOR AGONISTS - The invention provides novel indazole-carboxamide 5-HT | 10-14-2010 |
| 20110060122 | PROCESS FOR PREPARING GLYCOPEPTIDE PHOSPHONATE DERIVATIVES - Disclosed are processes for preparing glycopeptide phosphonate derivatives having an amino-containing side chain. Several of the process steps are conducted in a single reaction vessel without isolation of intermediate reaction products, thereby generating less waste and improving the overall efficiency and yield of the process. | 03-10-2011 |
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| 20080219648 | CIRCUIT AND METHOD FOR CONTROLLING THE ROTATING SPEED OF A BLDC MOTOR - A circuit and a method for controlling the rotating speed of a brushless direct current (BLDC) motor are provided, whose goal is solving the stall problem encountered by conventional BLDC motors driven by pulse width modulation (PWM). The circuit includes a closed-loop control mechanism for adjusting the duty cycle of the motor current of the BLDC motor, thus controlling the rotating speed of the motor. The closed-loop control is based on the comparison of a signal proportional to the actual rotating speed and another signal proportional to the predetermined target rotating speed. | 09-11-2008 |
| 20080316781 | BUCK CONVERTER LED DRIVER CIRCUIT - A buck converter LED driver circuit is provided. The driver circuit includes a buck power stage, a rectified AC voltage source, a voltage waveform sampler, and a control circuit. The buck power stage includes at least one LED and provides a first signal directly proportional to the current through the LED. The rectified AC voltage source is coupled to the buck power stage for driving the buck power stage. The voltage waveform sampler is coupled to the rectified AC voltage source for providing a second signal directly proportional to the voltage provided by the rectified AC voltage source. The control circuit is coupled to the voltage waveform sampler and the buck power stage for turning on and turning off the buck power stage according to a comparison between the first signal and the second signal. | 12-25-2008 |
| 20090257250 | SYNCHRONOUS RECTIFIER DC/DC CONVERTERS USING A CONTROLLED-COUPLING SENSE WINDING - A synchronous rectifier DC/DC converter is provided. The synchronous rectifier DC/DC converter includes a power transformer, a first diode, a first MOSFET, and a first controller. The power transformer includes a core, a primary winding, a secondary winding, and a sense winding. The primary winding is wrapped around the core and receives an input voltage of the synchronous rectifier DC/DC converter. The secondary winding is wrapped around the core and provides the energy of an output current of the synchronous rectifier DC/DC converter. The sense winding is wrapped around the core and provides a sense signal. The first diode is coupled to the secondary winding for rectifying the output current. The first MOSFET is coupled in parallel with the first diode. The first controller is coupled to the sense winding and the first MOSFET for turning on and turning off the first MOSFET according to the sense signal. | 10-15-2009 |
| 20110109249 | DIMMABLE LED LAMP AND DIMMABLE LED LIGHTING APPARATUS - A dimmable light-emitting diode (LED) lamp and a dimmable LED lighting apparatus thereof are provided. The dimmable LED lamp includes a bridge rectifier, a toggle detector, a sustain voltage supply circuit, a counter, an LED light source, and an LED lighting driver. The bridge rectifier receives a source alternating current (AC) voltage through a wall switch and provides a rectified direct current (DC) voltage. The toggle detector monitors a toggle action of the wall switch. The sustain voltage supply circuit provides a sustain voltage. The counter receives the sustain voltage for operation. Moreover, the counter stores and provides an counting value that changes when the toggle detector detects the toggle action. The LED lighting driver converts the rectified DC voltage to a constant current to drive the LED light source. The LED lighting driver also provides multi-level dimming to the LED light source according to the counting value. | 05-12-2011 |
| 20110234110 | LED DRIVER CIRCUIT - A light-emitting diode (LED) driver circuit is provided, which includes a transistor, a current regulator, a release diode, and a voltage clamping device. The transistor is coupled in series with an LED string. The LED string is coupled between the transistor and a bus voltage. The current regulator is coupled to the transistor for regulating the current through the transistor and the LED string to a predetermined current. The release diode has an anode coupled between the LED string and the transistor. The voltage clamping device is coupled to the cathode of the release diode for clamping the voltage level at the cathode of the release diode to a predetermined voltage. The voltage clamping device protects the transistor from breakdown when the transistor is turned off for dimming control. | 09-29-2011 |
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| 20090206876 | PROGRAMMABLE CORE FOR IMPLEMENTING LOGIC CHANGE - An apparatus comprising a plurality of fixed logic circuits, wherein each of the fixed logic circuits is configured to receive a plurality of input signals, perform combinational logic operations using the input signals, and produce at least one output signal, and wherein the combinational logic operations are substantially fixed; and a programmable logic core configured to functionally replace a selected subset of the plurality of fixed logic circuits, receive the input signals of the selected subset of the plurality of fixed logic circuits, perform logic operations on the input signals, and produce at least one output signal as the output signal of the selected subset of the plurality of fixed logic circuits, and wherein the logic operations are dynamically changeable. | 08-20-2009 |
| 20100057472 | METHOD AND SYSTEM FOR FREQUENCY COMPENSATION IN AN AUDIO CODEC - In a method and system for frequency compensation in an audio CODEC, a filter in a hardware audio CODEC may be configured based on power consumption and based on a frequency response of an active output device to which the filter is communicatively coupled. The filter may comprise a plurality of filter stages, which may be, for example, biquads, and the filter may be configured by enabling or disabling one or more of the stages. In this manner, power consumption of the filter may be managed by enabling and/or disabling one or more stages. Configuration of the filter may be performed dynamically depending on whether one or more audio output devices may be active. In this regard, which output device is active and its frequency response may be determined and filter coefficients may be reconfigured upon a change in which output device may be active. | 03-04-2010 |
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| 20080219431 | METHOD AND APPARATUS FOR ECHO CANCELLATION - A telephony system equipped with an echo cancellation module is disclosed. A hybrid interface circuit outputs an outbound signal to a wall jack while receiving an inbound signal from the wall jack. The inbound signal may contain a line echo of the outbound signal caused by the impedance mismatches in the hybrid interface circuit. A line echo canceller containing an adaptive filter is used to cancel the line echo in the inbound signal based on the learned line echo path characteristics captured in the training period. During a brief period after the telephony system is activated, the line echo canceller enters into a calibration mode wherein its adaptive filter is trained to learn the line echo path characteristics. During the calibration mode, the line echo canceller generates a calibration signal as the outbound signal and receives the line echo from the hybrid interface circuit to perform learning of the line echo path characteristics. | 09-11-2008 |
| 20080219433 | FULL DUPLEX HANDS-FREE TELEPHONE SYSTEM - A telephone system comprising an analog telephone and a full-duplex speakerphone adapter is disclosed. The analog telephone comprises an ordinary analog telephone subscriber circuit for transmitting and receiving analog signals and a handset for users. The full-duplex speakerphone adapter is coupled between the analog telephone and a central office, uses a subscriber loop interface circuit through the first telephone line to couple to the ordinary analog telephone subscriber circuit of the analog telephone and uses a telephone hybrid interface circuit through the second telephone line to couple to a wall jack to communicate with the central office. | 09-11-2008 |
| 20080219434 | METHOD AND APPARATUS FOR VOICE COMMUNICATION - A voice communication device with an integrated framework structure for echo cancellation and noise reduction is disclosed. A microphone receives a local input signal while a speaker is outputting a local output signal. The local input signal and output signal are all decomposed into a plurality of subband signals by filter banks for conducting individual processing of echo cancellation and noise reduction per subband. The subband echo canceller is followed by a DFT unit to split the cancellation result into a plurality of narrow frequency bins whereby the noise reduction is performed. The noise reduction results are recombined by an IDFT unit for residual echo removal in a subband non-linear processor. The final output is obtained from a synthesis filter bank that synthesizes the subband signals after echo cancellation and noise reduction into a full-band signal. | 09-11-2008 |
| 20080219463 | ACOUSTIC ECHO CANCELLATION SYSTEM - An embodiment of an acoustic echo cancellation system is disclosed. The system comprises an echo cancellation unit, a second filter and a subtraction unit. The echo cancellation unit comprises a first attenuator, a first filter and a first subtractor. The first attenuator has a first down-scaling factor for attenuating a first signal. The first filter generates a first echo signal estimate based on the attenuated first signal. The first subtractor generates a third signal by subtracting the first echo signal estimate from a second signal. The second filter generates a second echo signal estimate based on the first signal. The subtraction unit subtracts the second echo signal estimate from the third signal. | 09-11-2008 |
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| 20090039410 | Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing - An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency. | 02-12-2009 |
| 20090219776 | NON-VOLATILE MEMORY DEVICE WITH PLURAL REFERENCE CELLS, AND METHOD OF SETTING THE REFERENCE CELLS - A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells. | 09-03-2009 |
| 20100054043 | Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing - An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency. | 03-04-2010 |
| 20100254207 | Non-Volatile Memory Device with Plural Reference Cells, and Method of Setting the Reference Cells - A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells. | 10-07-2010 |
| 20110076816 | SPLIT GATE NON-VOLATILE FLASH MEMORY CELL HAVING A FLOATING GATE, CONTROL GATE, SELECT GATE AND AN ERASE GATE WITH AN OVERHANG OVER THE FLOATING GATE, ARRAY AND METHOD OF MANUFACTURING - An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency. | 03-31-2011 |
| 20110127599 | Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing - An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency. | 06-02-2011 |
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| 20080298466 | FAST DETECTION AND CODING OF DATA BLOCKS - A method of encoding a block of data. A first plurality of data in the block of data is assigned a worth based on a first algorithm. A second plurality of data, which is lower in frequency than the first plurality of data, in the block of data is assigned a worth according to a second algorithm. The block of data is assigned a worth based on the worth of the first plurality of data and the second plurality of data. The worth of the block of data is then compared to a threshold value, and subsequently one or more data values of the block of data are adjusted based on the comparison. | 12-04-2008 |
| 20090003453 | HIERARCHICAL PACKING OF SYNTAX ELEMENTS - A method of operation within an integrated circuit device having a plurality of processing lanes. A first sub-stream of data, having a variable length, is generated in a first one of the processing lanes. A second sub-stream of data, also having a variable length, is generated in a second one of the processing lanes. The first and second sub-streams are then output to form a single bitstream. | 01-01-2009 |
| 20120033739 | Error Concealment In A Video Decoder - The error concealment technique disclosed herein relates to the use of existing information by the decoder to conceal bitstream errors regardless of what the encoder does. Examples of existing information include, for example, the previous reference frame, macroblock information for the previous reference frames, etc. Another aspect of the system described herein relates to the steps that the encoder can take to enhance the decoder's ability to recover gracefully from a transmission error. Exemplary steps that can be taken by the encoder include intra walk around and sending GOB headers. Although these encoder techniques can provide greatly enhanced results, they are not strictly necessary to the system described herein. | 02-09-2012 |
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| 20100131265 | Method, Apparatus and Computer Program Product for Providing Context Aware Queries in a Network - A method for providing context aware queries in a network may include receiving a question directed to a question answering service from an originating node, routing the question to one or more candidate nodes selected based at least in part on context information associated with the question, receiving an answer to the question from at least one of the candidate nodes, and providing the answer to the originating node based at least in part on result parameters associated with the originating node. An apparatus and computer program product corresponding to the method are also provided. | 05-27-2010 |
| 20100271177 | METHOD AND APPARATUS FOR PROVIDING USER INTERACTION VIA TRANSPONDERS - An approach is provided for user interaction via transponders (e.g., near field communication (NFC) tag, radio frequency identification (RFID) tag, or contactless card) disposed on a dynamically reconfigurable display. Each transponder corresponds to an area of the display that is associated with one or more actions. The actions are dynamically updated based at least in part on the content presented on the respective area of the display. A user equipment containing a transponder reader detects a signal from one of the transponders to trigger the corresponding action. | 10-28-2010 |
| 20110103353 | METHOD AND APPARATUS FOR SELECTING A RECEIVER - In accordance with an example embodiment of the present invention, a method comprises identifying at least one receiver, selecting said at least one receiver by moving an apparatus according to at least one predetermined movement and sending data to said selected at least one receiver. | 05-05-2011 |
| 20110215903 | Apparatus and Associated Methods - In one or more embodiments described herein, there is provided an apparatus configured to identify a particular motion state of a portable electronic device, and vary the geographical location data sampling rate for the portable electronic device based on the identified particular motion state of the portable electronic device. | 09-08-2011 |
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| 20110159365 | TEMPLATE ELECTRODE STRUCTURES FOR DEPOSITING ACTIVE MATERIALS - Provided are examples of electrochemically active electrode materials, electrodes using such materials, and methods of manufacturing such electrodes. Electrochemically active electrode materials may include a high surface area template containing a metal silicide and a layer of high capacity active material deposited over the template. The template may serve as a mechanical support for the active material and/or an electrical conductor between the active material and, for example, a substrate. Due to the high surface area of the template, even a thin layer of the active material can provide sufficient active material loading and corresponding battery capacity. As such, a thickness of the layer may be maintained below the fracture threshold of the active material used and preserve its structural integrity during battery cycling. | 06-30-2011 |
| 20120070741 | HIGH CAPACITY BATTERY ELECTRODE STRUCTURES - Provided are battery electrode structures that maintain high mass loadings (i.e., large amounts per unit area) of high capacity active materials in the electrodes without deteriorating their cycling performance. These mass loading levels correspond to capacities per electrode unit area that are suitable for commercial electrodes even though the active materials are kept thin and generally below their fracture limits. A battery electrode structure may include multiple template layers. An initial template layer may include nanostructures attached to a substrate and have a controlled density. This initial layer may be formed using a controlled thickness source material layer provided, for example, on a substantially inert substrate. Additional one or more template layers are then formed over the initial layer resulting in a multilayer template structure with specific characteristics, such as a surface area, thickness, and porosity. The multilayer template structure is then coated with a high capacity active material. | 03-22-2012 |
