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| 20100262763 | DATA ACCESS METHOD EMPLOYED IN MULTI-CHANNEL FLASH MEMORY SYSTEM AND DATA ACCESS APPARATUS THEREOF - A data access method used in a multi-channel flash memory system includes: respectively writing a plurality of data into a plurality of buffer areas of a buffer unit through direct memory accessing; and sequentially reading the plurality of data from the plurality of buffer areas, and respectively and synchronously storing the plurality of read data into the plurality of flash memory units, wherein each of the plurality of data is a data block protected by an error correction code (ECC). | 10-14-2010 |
| 20100262764 | METHOD FOR ACCESSING STORAGE APPARATUS AND RELATED CONTROL CIRCUIT - A storage apparatus includes a first storage unit and at least a second storage unit. A method for accessing the storage apparatus generates a plurality of bad block lists regarding the plurality of the storage units, respectively, and according to at least one bad block indicated by a bad block list of the first storage unit, configures at least a good block in each second storage unit corresponding to the at least one bad block of the first storage unit as a replacement block of each second storage unit. Accordingly, the method generates a mapping result of each second storage unit according to a bad block list of the second storage unit and each replacement block, and accesses the storage apparatus according to the bad block list of the first storage unit and each mapping result. | 10-14-2010 |
| 20100318722 | DATA INTERLEAVING METHOD FOR STORAGE DEVICE AND RELATED STORAGE DEVICE - The present invention provides a data interleaving method for a storage device and a related storage device. The storage device comprises a plurality of non-volatile memory units, a buffer, and a processing unit. The method comprises: transmitting a plurality of first data required to be written to the plurality of non-volatile memory units to the buffer one by one; and respectively performing a plurality of interleaving operations to transmit the plurality of first data received by the buffer in sequence to the plurality of non-volatile memory units, respectively. The data interleaving method and the related storage device of the present invention only has to use one buffer, and thus the data interleaving method and the related storage device of the present invention can reduce requirement of buffer memory. | 12-16-2010 |
| 20110138109 | METHOD FOR WEAR-LEVELING AND APPARATUS THEREOF - A method for Wear-Leveling includes: utilizing a comparison circuit to compare an average erase count with an erase count of a first data block; and utilizing a first free block as a replacement for storing data content of the first data block so as to make the first data block become a free block when the erase count of the first data block is smaller than the average erase count. | 06-09-2011 |
| 20110138110 | METHOD AND CONTROL UNIT FOR PERFORMING STORAGE MANAGEMENT UPON STORAGE APPARATUS AND RELATED STORAGE APPARATUS - A storage apparatus has a first storage unit and a second storage unit. A method for performing storage management upon the storage apparatus includes: storing an input data into the first storage unit; and, while the input data is being stored into the first storage unit, checking whether the input data is continuous, wherein a portion of the input data which is not stored into the first storage unit yet will be stored into the first storage unit if the input data is found to be continuous, and the portion of the input data which is not stored into the first storage unit yet will be stored into the second storage unit if the input data is found to not be continuous. | 06-09-2011 |
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| 20090158763 | REFRIGERANT FLOATING EXPANSION APPARATUS - A refrigerant floating expansion apparatus including a main body, a standpipe, a float element and a separation element is provided. The main body includes a base plate and a pipe-shaped housing. The standpipe fixed on the base plate has a second pipe opening and a third pipe opening. The pipe wall of the standpipe has at least an opening near the second pipe opening. The float element surrounds the standpipe for controlling a fluid-passing area of the opening. The separation element surrounding the float element is disposed on the base plate and forms an inner path with the pipe-shaped housing. The separation element has several fluid passageways near the base plate. A high-pressure fluid entering the main body is guided to pass through the fluid passageways to move the float element for controlling the fluid-passing area of the opening. Then, the high-pressure fluid is transferred to a low-pressure fluid. | 06-25-2009 |
| 20100211228 | METHOD AND SYSTEM FOR CONTROLLING COMPRESSOR - In the present invention, a method and a system for controlling a compressor are provided. The method includes the steps of: providing a condenser connected to the compressor, and at least one evaporator connected to the condenser; measuring an inlet pressure and an outlet pressure of the compressor to obtain a flow rate of the condensate; determining a secure flow rate and a demanding flow rate based on a total number of the at least one evaporator; comparing at least two of the flow rate, the demanding flow rate and the secure flow rate with each other to obtain a compared result; and controlling the compressor based on the comparing result. | 08-19-2010 |
| 20100229587 | AIR CONDITIONING SYSTEM - An air conditioning system includes a first circulation module and a second circulation module. Two circulation modules are joined by a heat exchanger. The first circulation is a modular refrigeration system includes a compressor, expansion device, and heat exchangers. The second circulation module includes a main liquid refrigerant tank, a number of distributed liquid refrigerant tanks, liquid pumps and a plurality of indoor units which includes a heat exchange device and a vapor propelling device. The heat exchange device is connected to the main liquid tank. The vapor propelling device propels the working fluid in a saturated vapor state to the first heat exchanger, thus forming a working fluid loop. It can be switched between the heating and cooling modes. | 09-16-2010 |
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| 20090207574 | ELECTRONIC PACKAGE STRUCTURE - An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element. | 08-20-2009 |
| 20100102917 | INDUCTOR - An inductor includes a first core, a second core, a protruding structure, at least two gaps and a conducting wire. The first core has a protruding portion. The second core is disposed opposite to the first core. The protruding structure protrudes from the protruding portion of the first core and toward the second core. The at least two gaps are between the protruding portion of the first core and the second core. The conducting wire winds around at least one of the first and second cores. The conducting wire has a specific resistance value of 1.42 μΩm or lower. | 04-29-2010 |
| 20100308950 | CHOKE - A choke including a core and a hollow coil is provided. The core includes a first core body and a second core body. The first core body includes a pillar. The second core body is a flat plate and has an opening. An end of the pillar is suitable to be disposed in the opening and joined to the same. The hollow coil is fitted on the pillar. | 12-09-2010 |
| 20110057761 | PROTECTIVE DEVICE - A protective device including a substrate, a conductive section and a bridge element is provided. The conductive section is supported by the substrate, wherein the conductive section comprises a metal element electrically connected between first and second electrodes. The metal element serves as a sacrificial structure having a melting point lower than that of the first and second electrodes. The bridge element spans across the metal element in a direction across direction of current flow in the metal element, wherein the bridge element facilitates breaking of the metal element upon melting. | 03-10-2011 |
| 20110090648 | ELECTRONIC PACKAGE STRUCTURE - An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element. | 04-21-2011 |
| 20110278704 | THREE-DIMENSIONAL PACKAGE STRUCTURE - A three-dimensional package structure includes an energy storage element, a semiconductor package body and a shielding layer. The semiconductor package body has a plurality of second conductive elements and at least one control device inside. The energy storage element is disposed on the semiconductor package body. The energy storage element including a magnetic body is electrically connected to the second conductive elements. The semiconductor package body or the energy storage element has a plurality of first conductive elements to be electrically connected to an outside device. The shielding layer is disposed between the control component and at least part of the magnetic body to inhibit or reduce EMI (Electro-Magnetic Interference) from the energy storage element and to get a tiny package structure. The three-dimensional package structure is applicable to a POL (Point of Load) converter. | 11-17-2011 |
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| 20110073038 | GAS DISTRIBUTION PLATE AND APPARATUS USING THE SAME - The present invention provides a gas distribution plate for providing at least two gas flowing channel. In one embodiment, the gas distribution plate has a first flowing channel, at least a second flowing channel disposed around the first flowing channel, and a tapered opening communicating with the first and the second flowing channel. In another embodiment, the gas distribution plate has a first flowing channel passing through a first and a second surface of the gas distribution plate, a second flowing channel paralleling to the first surface and a third flowing channel disposed at the second surface and communicating with the second flowing channel. The ends of the first and the third flowing channel have a tapered opening respectively. Besides, the present further provides a gas distribution apparatus for allowing at least two separate gases to be delivered independently into a process chamber while enabling the gases to be mixed completely after entering the processing chamber. | 03-31-2011 |
| 20110094573 | Solar cell and method for fabricating the same - A solar cell and a method for fabricating the same are provided. The solar cell includes a first electrode, a second electrode, a photoelectric conversion layer and a non-conductive reflector. The first electrode including a nano-metal transparent conductive layer is disposed on a transparent substrate. The nano-metal transparent conductive layer substantially contacts with the photoelectric conversion layer. The second electrode is disposed between the photoelectric conversion layer and the transparent substrate. The photoelectric conversion layer is disposed between the first and the second electrodes. The non-conductive reflector is disposed on the first electrode. | 04-28-2011 |
| 20110247559 | GAS DISTRIBUTION SHOWER MODULE AND FILM DEPOSITION APPARATUS - A gas distribution shower module and a film deposition apparatus are provided. The gas distribution shower module includes a first distributor, a second distributor, a third distributor and a fourth distributor. The second distributor is under the first distributor, the third distributor is under the second distributor, the fourth distributor is under the third distributor, and a distance is between the fourth distributor and the third distributor. The third distributor is divided into an inner region and an outer region, and an area ratio of the inner region to the outer region is from 1:1 to 1:5. Furthermore, the third distributor has a plurality of gas holes in the inner region and the outer region, and an area ratio of the gas holes in the inner region to the gas holes in the outer region is from 1:1 to 1:5. | 10-13-2011 |
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| 20090040086 | DWA STRUCTURE AND METHOD THEREOF, DIGITAL-TO-ANALOG SIGNAL CONVERSION METHOD AND SIGNAL ROUTING METHOD - A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups. | 02-12-2009 |
| 20090110102 | SIGNAL ROUTING METHOD - A signal routing method adapted to a DWA structure is provided. The signal routing method at least includes following steps. An M-bit input digital signal is provided. The odd bit in the input digital signal is routed into a low-bit signal of an output digital signal, and the even bit in the input digital signal is routed into a high-bit signal of the output digital signal, wherein the output digital signal has M bits. | 04-30-2009 |
| 20100281222 | CACHE SYSTEM AND CONTROLLING METHOD THEREOF - A cache system and a method for controlling the cache system are provided. The cache system includes a plurality of caches, a buffer module, and a migration selector. Each of the caches is accessed by a corresponding processor. Each of the caches includes a plurality of cache sets and each of the cache sets includes a plurality of cache lines. The buffer module is coupled to the caches for receiving and storing data evicted due to conflict miss from a source cache line of a source cache set of a source cache among the caches. The migration selector is coupled to the caches and the buffer module. The migration selector selects, from all the cache sets, a destination cache set of a destination cache among the caches according to a predetermined condition and causing the evicted data to be sent from the buffer module to the destination cache set. | 11-04-2010 |
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| 20080237761 | SYSTEM AND METHOD FOR ENHANCING LIGHT SENSITIVITY FOR BACKSIDE ILLUMINATION IMAGE SENSOR - A system and method for enhancing light sensitivity of a back-side illumination image sensor are described. An integrated circuit includes a substrate and an image sensor device comprising at least one transistor formed over a first surface of the substrate and a photosensitive region. A color filter is disposed over a second surface of the substrate opposite the first surface thereof. A micro-lens structure is disposed between the second surface of the substrate and the color filter. | 10-02-2008 |
| 20080246152 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A semiconductor device with a bonding pad is provided. The semiconductor device includes a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are disposed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is disposed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad, and the first substrate is exposed through an opening in the lowermost metal pattern. | 10-09-2008 |
| 20090124073 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern. | 05-14-2009 |
| 20090130814 | SEMICONDUCTOR METHODS - A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor. | 05-21-2009 |
| 20100062611 | Method and Apparatus for Thinning a Substrate - Provided is a method for fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a backside, where active or passive devices are formed in the front side, rotating the semiconductor substrate, and etching the backside of the semiconductor substrate by introducing a first etchant while the substrate is rotated, the first etchant including an R—COOH. | 03-11-2010 |
| 20100151615 | METHODS FOR FABRICATING IMAGE SENSOR DEVICES - Image sensor devices and methods for fabricating the same are provided. An exemplary embodiment of an image sensor device comprises a support substrate. A passivation structure is formed over the support substrate. An interconnect structure is formed over the passivation structure. A first semiconductor layer is formed over the interconnect structure, having a first and second surfaces, wherein the first and second surfaces are opposing surfaces. At least one light-sensing device is formed over/in the first semiconductor layer from a first surface thereof. A color filter layer is formed over the first semiconductor layer from a second surface thereof. At least one micro lens is formed over the color filter layer. | 06-17-2010 |
| 20110177668 | METHOD OF MAKING A THIN FILM RESISTOR - A method of making a thin film resistor includes: forming a doped region in a semiconductor substrate; forming a dielectric layer over the substrate; forming a thin film resistor over the dielectric layer; forming a contact hole in the dielectric layer before annealing the thin film resistor, wherein the contact hole exposes a portion of the doped region; and performing rapid thermal annealing on the thin film resistor after forming the contact hole. | 07-21-2011 |
| 20110318898 | HARD MASK FOR THIN FILM RESISTOR MANUFACTURE - Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer. | 12-29-2011 |
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| 20090030600 | Method of providing navigation information by recalculating navigation route - A method of providing navigation information by recalculating a navigation route is used in a global positioning device. The method reads an original navigation route first. If another new navigation route can be read again, it shows that the global positioning device is deviated from the original navigation route, and route data of the original navigation route and the new navigation route are compared to generate a comparing information such as an overlapped position of the two navigation routes, and the time or distance required to return to the original new navigation route from the new navigation route and display the comparing information on the global positioning device to remind the users. The present invention can greatly reduce the tension of a user who is not familiar with the routes and road conditions. | 01-29-2009 |
| 20090177374 | Method for real-time updating background weather patern of electronic map - A method for a navigation device to change a background weather pattern of an electronic map comprises steps of: reading a plurality of positioning signals received by a positioning module and calculating a current location of the navigation accordingly; reading from a map database and a real-time weather database, respectively, an electronic map and a background weather pattern that correspond to the current location, and outputting the electronic map and the background weather pattern corresponding to the current location on a display device; determining whether it is necessary to change the electronic map corresponding to the current location; and when it is necessary, reading from the real-time weather database a background weather pattern corresponding to an updated current location and replacing the presently displayed electronic map and background weather pattern with an electronic map and a background weather pattern corresponding to the updated current location. | 07-09-2009 |
| 20090177387 | Method of planning pedestrian navigation route - The present invention discloses a method of planning a pedestrian navigation route, and the method is applied to a pedestrian navigation device. The pedestrian navigation device includes a map database having a pedestrian road data and a driving route data of at least one public transportation means. In the method, when the pedestrian navigation device is planning a pedestrian navigation route, the pedestrian navigation device reads start position information and end position information, plans a pedestrian road and a driving route of different public transportation means between a start position and an end position according to a pedestrian road data and a driving route data, and then compiles the same into a pedestrian navigation route. The invention allows a pedestrian to reach an end position (or destination) selectively by walking along the planned pedestrian road or taking a ride of the selected public transportation means. | 07-09-2009 |
| 20090216436 | NAVIGATION DEVICE CAPABLE OF DISPLAYING LOCAL LABELS AND METHOD THEREOF - The present invention discloses a navigation device which is capable of displaying local labels and a method thereof. The navigation device comprises a map database, a navigation module, a positioning module and a display interface. The map database is capable of storing at least one electronic map, comprising a plurality of map blocks. The navigation module is capable of providing a navigation route located on at least one of the plurality of map blocks, and the navigation route comprises a starting point, a plurality of local labels and a destination. The local labels are located from the starting point to the destination in order. The positioning module is capable of providing at least one positioning location. The display interface is capable of displaying at least one of the plurality of map blocks where the navigation route is located on according to the positioning location, and displays at a next local label on the map blocks. The next local label is located on one end of the navigation route toward a direction of the destination. | 08-27-2009 |
| 20110112757 | Navigation System and Method Thereof - A navigation system includes a storage module, a positioning module, a time module, and an integration module. The integration module is electrically connected to the storage module, the positioning module and the time module, and compares a navigation keyword with a plurality of landmark names of a map data stored in the storage module. When at least one of the landmark names is found to be partially or completely the same as the navigation keyword and is currently in opening hours, the integration module selects one of these landmark names and creates a navigation path directed to the selected landmark name based on the orientation data of the selected landmark name, positioning information output by the positioning module, and time information output by the time module. A navigation method implemented based on the above navigation system is also disclosed. | 05-12-2011 |
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| 20090222785 | METHOD FOR SHAPE AND TIMING EQUIVALENT DIMENSION EXTRACTION - An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout. | 09-03-2009 |
| 20100095253 | TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 04-15-2010 |
| 20110023002 | DOUBLE PATTERNING FRIENDLY LITHOGRAPHY METHOD AND SYSTEM - A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC. | 01-27-2011 |
| 20110124193 | CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout. | 05-26-2011 |
| 20110161907 | Practical Approach to Layout Migration - The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node. | 06-30-2011 |
| 20110197168 | DECOMPOSING INTEGRATED CIRCUIT LAYOUT - Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed. | 08-11-2011 |
| 20110204470 | METHOD, SYSTEM, AND APPARATUS FOR ADJUSTING LOCAL AND GLOBAL PATTERN DENSITY OF AN INTEGRATED CIRCUIT DESIGN - An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density. | 08-25-2011 |
| 20110214101 | METHOD OF THERMAL DENSITY OPTIMIZATION FOR DEVICE AND PROCESS ENHANCEMENT - The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance. | 09-01-2011 |
| 20110217630 | INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material. | 09-08-2011 |
| 20110230998 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
| 20110231804 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
| 20110243424 | METHOD AND APPARATUS FOR MONITORING MASK PROCESS IMPACT ON LITHOGRAPHY PERFORMANCE - The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern. | 10-06-2011 |
| 20110245949 | METHOD AND APPARATUS OF PATTERNING SEMICONDUCTOR DEVICE - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 10-06-2011 |
| 20110252387 | METHOD AND APPARATUS FOR REDUCING IMPLANT TOPOGRAPHY REFLECTION EFFECT - Embodiments of the present disclosure provide methods and apparatuses for integrated circuits. An exemplary integrated circuit (IC) method includes providing an IC design layout that includes a design feature; determining a dimensional difference between the design feature and a corresponding developed photoresist feature of a photoresist layer; modifying the CD of the design feature to compensate for the difference, thereby generating a modified IC design layout; and making a mask using the modified IC design layout. | 10-13-2011 |
| 20110289466 | Table-Based DFM for Accurate Post-Layout Analysis - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 11-24-2011 |
| 20110296360 | METHOD FOR CHECKING AND FIXING DOUBLE-PATTERNING LAYOUT - A method and system checks a double patterning layout and outputs a representation of G0-rule violations and critical G0-spaces. The method includes receiving layout data having patterns, determining whether each distance between adjacent pattern elements is a G0-space, find all G0-space forming a G0-rule violation, finding all G0-space that are critical G0-spaces, and outputting a representation of G0-rule violations and critical G0-spaces to an output device. By resolving G0-rule violations and critical G0-spaces, a design checker can effectively generate a double patterning technology (DPT) compliant layout. | 12-01-2011 |
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| 20090233112 | MULTILAYER ZINC OXIDE VARISTOR - Enclosed is a multilayer zinc oxide (ZnO) varistor having a body portion, internal electrodes extending from both sides to the interior of the body portion respectively, and terminal electrodes disposed at both sides of the body portion. The multilayer zinc oxide is characterized in that: the components of said body portion include at least 90 mole % ZnO, 0.1 to 5.0 mole % antimony oxide functional additives, 0.01 to 1.0 mole % praseodymium oxide functional additives, and 0.01 to 10.0 wt. % glass; the sum amount of these metal oxides is less than 99.95 mole %. | 09-17-2009 |
| 20110316658 | THIN TYPE COMMON MODE FILTER AND METHOD OF MANUFACTURING THE SAME - A thin type common mode filter includes an insulating flexible substrate, a first magnetic material layer, a first coil leading layer, a coil main body multi-layer, a second coil leading layer, and a second magnetic material layer. The first coil leading layer is formed on a first surface of the flexible substrate, and the first coil leading layer is formed on a second surface of the flexible substrate opposite to the first surface. The coil main body multi-layer, the second coil leading layer, and the second magnetic material layer are sequentially stacked on the first coil leading layer. | 12-29-2011 |
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| 20090092772 | Extreme low resistivity light attenuation anti-reflection coating structure and method for manufacturing the same - An extreme low resistivity light attenuation anti-reflection coating structure with a surface protective layer includes a substrate, a coating module, and a composed protection coating layer. The coating module is formed on a front surface of the substrate. The coating module is composed of a plurality of silicon carbide compound coating layers and a plurality of metal coating layers that are alternately stacked with each other. The composed protection coating layer is formed on the coating module. | 04-09-2009 |
| 20090092808 | Extreme low resistivity light attenuation anti-reflection coating structure and method for manufacturing the same - An extreme low resistivity light attenuation anti-reflection coating with a transparent surface conductive layer includes a substrate, a coating module, and a composed protection coating layer. The coating module is formed on a front surface of the substrate. The coating module is composed of a plurality of mixture coating layers and a plurality of metal coating layers that are alternately stacked with each other. Each mixture coating layer is composed of Ti-based oxide and carbon. The composed protection coating layer is formed on the coating module. | 04-09-2009 |
| 20090092825 | Extreme low resistivity light attenuation anti-reflection coating structure and method for manufacturing the same - A extreme low resistivity light attenuation anti-reflection coating structure includes a substrate, a coating module, and a composed protection coating layer. The coating module is formed on a front surface of the substrate. The coating module is composed of a plurality of Ti-based oxide coating layers and a plurality of metal coating layers that are alternately stacked with each other. The composed protection coating layer is formed on the coating module. | 04-09-2009 |
| 20090092850 | Extreme low resistivity light attenuation anti-reflection coating structure and method for manufacturing the same - An extreme low resistivity light attenuation anti-reflection coating with a transparent surface conductive layer includes a substrate, a coating module, and a composed protection coating layer. The coating module is formed on a front surface of the substrate. The coating module is composed of a plurality of mixture coating layers and a plurality of metal coating layers that are alternately stacked with each other. Each mixture coating layer is composed of silicon carbide compound and Ti-based oxide. The composed protection coating layer is formed on the coating module. | 04-09-2009 |
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| 20100172191 | Voltage Regulation Method and Memory Applying Thereof - A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written data, is counted, wherein the set of written data is written into the set of memory cells. Next, a second value, which is for indicating an amount of data having the specific data value in a set of read data, is counted, wherein the set of read data is obtained by reading the set of written data. Then, a regulating voltage is determined according to a difference between the first and second values. After that, the word line voltage is regulated to be a sum of the word line voltage and the regulating voltage. | 07-08-2010 |
| 20110058430 | Voltage Regulation Method and Memory Applying Thereof - A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written data, is counted, wherein the set of written data is written into the set of memory cells. Next, a second value, which is for indicating an amount of data having the specific data value in a set of read data, is counted, wherein the set of read data is obtained by reading the set of written data. Then, a regulating voltage is determined according to a difference between the first and second values. After that, the word line voltage is regulated to be a sum of the word line voltage and the regulating voltage. | 03-10-2011 |
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| 20100026410 | TRANSCEIVER DEVICE AND IMPEDANCE MATCHING METHOD - A transceiver device and an impedance matching method are provided. In the impedance matching method, a plurality of matching modes is set. Each matching mode includes a default impedance and a corresponding default power. In addition, one of the matching modes is selected for outputting a transmission signal to a load. Besides, a response signal derived from the transmission signal is received. Further, whether the default impedance is matched with an impedance of the load or not is determined according to a parameter of the response signal. Thereby, the echo signal can be restrained from being generated. | 02-04-2010 |
| 20100029346 | TRANSCEIVER DEVICE AND POWER SAVING METHOD THEREOF - A transceiver device and a power saving method thereof are provided. The transceiver device includes a transmitter, a receiver, and a control module. The control module is coupled to the transmitter and the receiver. After the control module lowers the output power of either the transmitter, the receiver, or both of them, the control module checks a signal transmission between the transceiver device and a far-end device is normal or not. When the signal transmission between the transceiver device and the far-end device is abnormal, the control module readjusts the output power of the transmitter, the receiver, or both of them. Thereby, the power consumption of the transceiver device is decreased. | 02-04-2010 |
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| 20100315580 | THIN FILM TRANSISTOR ARRAY SUBSTRATE, DISPLAY PANEL, LIQUID CRYSTAL DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display panel having a pixel region and a sensing region includes a first substrate, a second substrate and a display medium layer. A plurality of pixel structures and at least one photo-voltaic cell device are disposed on the first substrate. The pixel structures are arranged in the pixel region in array, and each of the pixel structures includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor. The photo-voltaic cell device disposed in the sensing region includes a doped semiconductor layer, a transparent electrode layer, a first type doped silicon-rich dielectric layer and a second type doped silicon-rich dielectric layer. The first type doped silicon-rich dielectric layer and the second type doped silicon-rich dielectric layer are disposed between the doped semiconductor layer and the transparent electrode layer. The display medium layer is disposed between the first substrate and the second substrate. | 12-16-2010 |
| 20110156043 | THIN FILM TRANSISTOR - A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a gate insulating layer, a silicon-rich channel layer, a source, and a drain. The gate is disposed on the substrate. The gate insulator is disposed over the gate. The silicon-rich channel layer is disposed above the gate, wherein the material of the silicon-rich channel layer is selected from a group consisting of silicon-rich silicon oxide (Si-rich SiOx), silicon-rich silicon nitride (Si-rich SiNx), silicon-rich silicon oxynitride (Si-rich SiOxNy), silicon-rich silicon carbide (Si-rich SiC) and silicon-rich silicon oxycarbide (Si-rich SiOC). The content (concentration) of silicon of the silicon-rich channel layer within a film depth between 10 nm to 170 nm ranges from about 1E23 atoms/cm | 06-30-2011 |
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| 20090096775 | Differential signal interfacing device and related method - The present invention provides a differential signal interfacing device, including a reduced swing differential signaling (RSDS) transmitter and a plurality of RSDS receivers, in order to improve RSDS signal capacity. The RSDS transmitter is coupled to the plurality of RSDS receivers via a bus and transmits a RSDS signal in a discontinuous manner. The plurality of RSDS receivers receives the RSDS signal for signals of different types. | 04-16-2009 |
| 20090110138 | Shift Register Circuit - A shift register circuit includes a plurality of bit register units, coupled in series, for transferring an input signal among the plurality of bit register units to sequentially output the input signal to a plurality of data output terminals according to a control signal and a clock signal, wherein the number of the plurality of data output terminals is greater than that of the plurality of bit register units, and a control unit for generating the control signal to control transference of the input signal. | 04-30-2009 |
| 20090309860 | Driving Method and Related Device for Reducing Power Consumption of LCD - A driving method is provided for reducing power consumption of a liquid crystal display. The driving method includes steps of sequentially receiving first data and second data, determining whether the second data is the same as the first data, and controlling a data-line driving circuit not to read in driving data corresponding to the second data when the second data is the same as the first data. | 12-17-2009 |
| 20100045657 | Driving Device for Liquid Crystal Display - A driving device of a liquid crystal display (LCD) utilized for preventing noises of a clock signal from causing error operation of a shift register is disclosed. The driving device includes a shift register, a reception terminal, a noise elimination circuit and a control signal generation circuit. The reception terminal is utilized for receiving a first clock signal. The noise elimination circuit is coupled to the reception terminal, and is utilized for eliminating noises of the first clock signal and delaying the first clock signal for a preset time to generate a second clock signal. The control signal generation circuit is coupled to the reception terminal, the noise elimination circuit and the shift register, and is utilized for generating a first control signal and a second control signal to control the shift register. | 02-25-2010 |
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| 20100109043 | METHODS AND STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event. | 05-06-2010 |
| 20100109076 | STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A first doped region of the first conductivity type and a second doped region of the second conductivity type are located in the second well region. A first transistor includes the first doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event. | 05-06-2010 |
| 20110216454 | ELECTROSTATIC DISCHARGE PROTECTORS HAVING INCREASED RC DELAYS - An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area. | 09-08-2011 |
