Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Liu, AZ
Belinda Liu, Mesa, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090115744 | ELECTRONIC FREEBOARD WRITING SYSTEM - A writing system includes a pen with a two-dimensional optical sensor and a three dimensional acceleration sensor positioned to indicate movement of the pen. A calibrator is coupled to receive path coordinate signals from the two-dimensional optical sensor and the three dimensional acceleration sensor. The calibrator and the two-dimensional optical sensor and the three dimensional acceleration sensor are configured to operate in one of two modes, a contactable mode of operation wherein both the two-dimensional optical sensor and the three dimensional acceleration sensor supply path coordinate signals to the coordinator and a contactless mode of operation wherein only the three dimensional acceleration sensor supplies path coordinate signals to the coordinator. | 05-07-2009 |
Chun-Li Liu, Mesa, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090115001 | MOS DEVICES WITH MULTI-LAYER GATE STACK - An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor. | 05-07-2009 |
| 20100155825 | TRANSISTOR DEVICES WITH NANO-CRYSTAL GATE STRUCTURES - Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer. | 06-24-2010 |
Chun-Li Liu, Scottsdale, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090146191 | LOW LEAKAGE SCHOTTKY CONTACT DEVICES AND METHOD - Method and apparatus are described for semiconductor devices. The method ( | 06-11-2009 |
| 20100059860 | COUNTER-DOPED VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 03-11-2010 |
| 20110156051 | SEMICONDUCTOR DEVICES WITH LOW LEAKAGE SCHOTTKY CONTACTS - Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced. | 06-30-2011 |
Cindy Liu, Flagstaff, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20110092385 | COMPOSITIONS AND METHODS TO DETECT INFLUENZA VARIANTS - Methods and kits used in the detection of variants of the Influenza virus are disclosed, including variants that are resistant to treatment with antiviral compositions. | 04-21-2011 |
| 20110263462 | METHODS AND KITS USED IN THE DETECTION OF FUNGUS - The invention encompasses methods of using quantitative PCR to detect fungal organisms in clinical and environmental samples and to generate standards that allow the quantification of fungal organisms in the samples. | 10-27-2011 |
Daming Liu, Tucson, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090251697 | LASER EMITTER MODULES AND METHODS OF ASSEMBLY - Embodiments are directed to laser emitter modules and methods and devices for making the modules. Some module embodiments are configured to provide hermetically sealed enclosures that are convenient and cost effective to assemble and provide for active alignment of optical elements of the module. | 10-08-2009 |
| 20120177074 | HIGH RELIABILITY LASER EMITTER MODULES - Embodiments are directed to laser emitter modules, or subassemblies thereof, and methods and devices for making or using the modules. Some module embodiments are configured to provide hermetically sealed enclosures that are thermally stable during use, highly reliable in adverse environments, convenient and cost effective to manufacture or any combination of the foregoing. | 07-12-2012 |
Henry Z. Liu, Tucson, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090282297 | Leveled Logging Data Automation for Virtual Tape Server Applications - A method, system, and program product for a VTS subsystem's logging server to optimize applications' logging data entries where applications use the logging service. More specifically, in certain embodiments, the system comprises logic executed within a VTS subsystem to which a tape library subsystem is attached. The logic controls VTS subsystem applications' logging data entry strategy through applications' configured logging level, log entry category, and a cache buffer. The logic not only dynamically balances applications' logging request but also maximizes the availability of system information. | 11-12-2009 |
Henry Zheng Liu, Tucson, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20080246638 | APPARATUS AND METHOD TO ENCODE BINARY DATA INTO TRINARY DATA - An apparatus and method are disclosed to encode binary data into trinary data. Applicants' method provides binary data, and encodes that binary data into trinary data. By “binary data,” Applicants mean a plurality of bits, wherein each of those bits comprises a value selected from the group consisting of a first value and a second value. By “trinary data,” Applicants mean a plurality of bits, wherein each of those bits comprises a value selected from the group consisting of a first value, a second value, and a third value. The trinary data may be stored in ROM optical disks, nano-sized indentations in a thin-film, or multi-level magnetic storage. The trinary data may be also transmitted via three light levels in an optical communications network. | 10-09-2008 |
| 20090086299 | APPARATUS AND METHOD TO ENCODE INFORMATION HOLOGRAPHICALLY - A method to encode information holographically, wherein the method provides information, and generates a plurality of data images, wherein each data image comprises a portion of the information. The method holographically encodes each of the plurality of data images in a holographic data storage medium, generates a plurality of identifiers, and associates a different one of the plurality of identifiers with a different one of the plurality of data images. The method forms a directory image reciting each of plurality of identifiers, encodes the directory image in a non-holographic data storage medium, and holographically encodes the directory image in the holographic data storage medium. | 04-02-2009 |
| 20100027401 | RUN LENGTH LIMITED ENCODING OF DATA INTO A 5X5 MATRIX FOR RECORDING INTO A HOLOGRAPHIC MEDIUM - Holographic recording drives encode data for recording into a holographic medium. The steps comprise run length limited encoding three bytes of data into 5×5 matrix information, the data subject to a 4-byte error correction code; and providing the 5×5 matrix information to a spatial light modulator (SLM), as a portion of a two-dimensional pixel matrix of the spatial light modulator, for recording into a holographic image on the holographic medium. | 02-04-2010 |
John Liu, Gilbert, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20100186840 | MULTI-VALVE MICROFLUIDIC DEVICES AND METHODS - Multi-valve autoregulatory microfluidic devices and methods are described. The described devices and methods offer improved performance and new means of tuning autoregulatory effects in microfluidic devices. | 07-29-2010 |
Jong Liu, Scottsdale, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20100329846 | TURBINE ENGINE COMPONENTS - A turbine engine component includes a wall, a main opening, and two clusters of two or more auxiliary openings. The wall includes cool and hot air sides. The main opening extends between the cool air side and the hot air side and has an inlet and an outlet. The inlet is formed on the cool air side, and the outlet is formed on the hot air side. The first cluster of two or more auxiliary openings extends from the main opening to the hot air side. The second cluster of two or more auxiliary openings extends from the main opening to the hot air side. The main opening may be cylindrical or conical with a converging passage extending from the cool air side to the hot air side. The converging main opening may enhance flow through the auxiliary openings especially at high blowing ratios. | 12-30-2010 |
| 20110123312 | GAS TURBINE ENGINE COMPONENTS WITH IMPROVED FILM COOLING - An engine component includes a body; and a plurality of cooling holes formed in the body. At least one of the cooling holes has cross-sectional shape with a first concave portion and a first convex portion. | 05-26-2011 |
| 20110311369 | GAS TURBINE ENGINE COMPONENTS WITH COOLING HOLE TRENCHES - An engine component includes a body having an interior surface and an exterior surface; a cooling hole formed in the body and extending from the interior surface to the exterior surface; and a concave trench extending from the cooling hole at the exterior surface of the body in a downstream direction. | 12-22-2011 |
Katherine Liu, Tucson, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090173385 | METHODS TO BOND OR SEAL GLASS PIECES OF PHOTOVOLTAIC CELL MODULES - The apparatus and methods of the present disclosure, in a broad aspect, provide novel ways for bonding or sealing pieces of glass of photovoltaic cell modules. These include providing the first piece of glass having a planar surface, providing the second piece of glass having a second planar surface, providing a photovoltaic cell between the first piece of glass and second piece of glass, providing an amount of solder to at least one solder contact area disposed on at least one of the first or second pieces of glass, bringing the first and second pieces of glass into contact at the at least one solder contact area, and heating the solder to about the melting point or working point of the solder to provide the first and second pieces of glass with a bond or seal at the at least one solder contact area. | 07-09-2009 |
Katherine X. Liu, Tucson, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090324177 | FIBER OPTIC CABLE SPLICE AND CABLE RECONSTRUCTION - A new fiber optic cable splice for splicing optical fiber cables together and reconstructing fiber-optic cable that provide substantially enhanced reliability and broadened operating temperature range is disclosed. The disclosed cable splice offer reliable and user friendly solutions to applications in many harsh environments such as avionics, field vehicles, and defense related instrumentation. The cable splice consists of a preassembled one piece splice core and outer mechanical and thermal shielding layers. A simple splicing procedure and key fixtures are also disclosed. | 12-31-2009 |
Kungwel Liu, Chandler, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090287402 | VIRTUAL TRAFFIC SENSORS - Techniques are described for virtual traffic sensors (VTS). In an implementation, an electronic device provides a variety of functionality including at least functionality to determine position. The electronic device may be further configured to ascertain locations of one or more virtual traffic sensors. In at least some embodiments, locations of virtual traffic sensors are determined by the electronic device using a variety of VTS criteria. Using a determined position, the electronic device may detect proximity to the virtual traffic sensors. The electronic device may collect traffic related data when in proximity to the one or more virtual traffic sensors. The electronic device may then communicate the collected traffic data over a suitable network connection to a service provider. | 11-19-2009 |
| 20090287405 | TRAFFIC DATA QUALITY - Techniques are described for traffic data quality. In an implementation, an electronic device provides a variety of functionality including functionality to determine position. The device may use determined position to ascertain geographic locations as collection points where traffic related data may be collected. In at least some embodiments, traffic data quality techniques combining both device side and server side technique are applied to data collected at the collections points. In an embodiment, communication of collected data by the device may be delayed to enable additional observations of vehicle movement, routing, position, and so forth. The additional observations during the delay enable the device to determine the validity of the collected data. | 11-19-2009 |
| 20100049397 | FUEL EFFICIENT ROUTING - Techniques are described to determine a fuel-efficient route for a vehicle. In an implementation, a determination is made, based on the one or more characteristics of the vehicle, as to a route between an identified location and a designated location that would cause the vehicle to consume a lesser amount of fuel when traveling between the identified and designated locations. Accordingly, the route may be represented, such as for use in navigating to the designated location. | 02-25-2010 |
| 20110153189 | HISTORICAL TRAFFIC DATA COMPRESSION - A device and method for calculating information regarding a route to a destination. The device may include a computer-readable memory element on which is stored a plurality of templates comprising historical speed values for a quantity of time segments and a map database including data for a plurality of road segments associated with template codes identifying one or more of the templates. The device may also include a processing device for accessing the map database to determine a historical speed value for one or more selected road segments. The historical speed value may be used for calculating an estimated amount of time to complete a selected route, a route to the destination that takes the least amount of time, and/or a predicted time of arrival at the destination. | 06-23-2011 |
| 20110207455 | METHOD AND APPARATUS FOR ESTIMATING CELLULAR TOWER LOCATION - A method and apparatus for collecting and analyzing cellular identification (ID) numbers at various geographic locations to estimate cellular tower locations. The method may include collecting cellular ID numbers obtained by collection mobile devices at a plurality of geographic locations then calculating minimum bounding circles encompassing a set of geographic location points with the same cellular identification numbers. If the cellular ID number of a set of location points indicates that the cellular tower is omni-directional, a center of the minimum bounding circle is an estimated cellular tower location. If the cellular ID number indicates that the cellular tower is multi-sector, the apparatus may calculate the estimated cellular tower location as the location at which lines that extend from the centers of a plurality of related minimum bounding circles intersect with each other to form equal angles. | 08-25-2011 |
| 20120124125 | AUTOMATIC JOURNAL CREATION - Techniques are described that facilitate the automatic creation of journals that may include a variety of related content. Journal creation functionality may be furnished by a server to one or more client devices to create journals of content that include content from one or more content sources. The content provided by the content sources includes tags (e.g., metadata) describing the content. Thus, a client device may furnish a request to a server to create a journal of content. The request includes an attribute to relate the content of the journal. The server causes content to be associated with the journal from one or more computer-readable content sources accessible by the server by associating one or more of the content tags with the attribute for one or more existing journals and thereafter creating the journal using the processor by causing content from the one or more existing journals to be associated with the journal, the associated content having tags associated with the attribute. | 05-17-2012 |
Lei Liu, Tucson, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20080219188 | Home Media Switch - A media switch includes a backplane. A controller module is connected to the backplane for transferring a user command to a media device. A set of audio/video signal busses are connected to the backplane for transferring signals. A power bus is connected to the backplane for supplying power. A bus interface is connected to the bus to provide a connection point for the media device. A bus switch is positioned between the interface and the bus for transferring signals to the bus. The switch is operated by the controller module. A command bus is connected to the backplane for transferring a user command to the media device via a command interface. | 09-11-2008 |
| 20100180131 | POWER MANAGEMENT MECHANISM FOR DATA STORAGE ENVIRONMENT - A method, system, and computer program product for facilitating power instability in a central electronics complex (CEC) of data storage computing environment in advance of a potential power failure is provided. Upon receipt of a first early power off warning (EPOW) signal indicating power instability, a first priority of execution of a first data storage task to be performed pursuant to a new data storage request is decreased, while a second priority of execution of a second data storage task to destage data in nonvolatile storage (NVS) to disk is increased. Upon receipt of a second EPOW signal indicating power failure, a system shutdown procedure is executed. | 07-15-2010 |
| 20120151167 | SYSTEMS AND METHODS FOR MANAGING READ-ONLY MEMORY - Systems, methods, and computer storage mediums for managing read-only memory are provided. A system includes a memory device including a real memory and a tracking mechanism configured to track relationships between multiple virtual memory addresses and real memory. The system further includes a processor configured to perform the below method and/or execute the below computer program product. One method includes mapping a first virtual memory address to a real memory in a memory device and mapping a second virtual memory address to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory. One computer storage medium includes a computer program product for performing the above method. | 06-14-2012 |
| 20120233375 | ADJUSTMENT OF POST AND NON-POST PACKET TRANSMISSIONS IN A COMMUNICATION INTERCONNECT - In a communication interconnect such as PCIe which favors post transmissions such as write requests over non-post transmissions such as read requests and completions, methods and systems for shortening the delay for non-post transmissions while maintaining fairness among the post transmissions. Undispatched non-post transmission requests are monitored on a running basis; and when a running value of the undispatched non-post transmission requests exceeds a threshold; ones of the post transmission requests are randomly dropped. | 09-13-2012 |
| 20120254498 | SYSTEMS AND METHODS FOR MANAGING READ-ONLY MEMORY - A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory. | 10-04-2012 |
Lucy Ning Liu, Peoria, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20130013086 | DYNAMIC MODEL GENERATION FOR IMPLEMENTING HYBRID LINEAR/NON-LINEAR CONTROLLER - A method of dynamic model selection for hybrid linear/non-linear process control includes developing a plurality of process models including at least one linear process model and at least one non-linear process model from inputs including dynamic process data from a processing system that runs a physical process. At least two of the plurality of process models are selected based on a performance comparison based on at least one metric, wherein the selected process models number less than a number of the plurality of process models received. A multi-model controller is generated that includes the selected process models. The physical process is simulated using the multi-model controller by applying the selected process models to obtain closed loop performance test data for each of the selected models. The performance test data is compared. A selected process model is then selected. | 01-10-2013 |
Pilin Liu, Chandler, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20110293962 | SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE - Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed. | 12-01-2011 |
Xinyao Liu, Tempe, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20110159594 | NUCLEIC ACIDS, BACTERIA, AND METHODS FOR DEGRADING THE PEPTIDOGLYCAN LAYER OF A CELL WALL - The invention encompasses compositions and methods for degrading the peptidoglycan layer of a cell wall. In particular, the invention encompasses compositions and methods for degrading the peptidoglycan layer of the cell wall of a gram-negative bacterium. | 06-30-2011 |
Xinyao Liu, Chandler, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20120237987 | BACTERIUM FOR PRODUCTION OF FATTY ACIDS - The present invention encompasses a bacterium that produces fatty acids. | 09-20-2012 |
Yi-Feng Liu, Chandler, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20110060931 | POWER MEASUREMENT TECHNIQUES OF A SYSTEM-ON-CHIP (SOC) - A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts. | 03-10-2011 |
Yueli Liu, Gilbert, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20120161330 | DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS - Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. | 06-28-2012 |